Abstract: A solid-state image pickup apparatus includes a first structure having a first substrate, and a pixel region including a plurality of pixels which is formed in the first substrate, outputs pixel signals according to amounts of electric charges generated by photoelectric conversion, and is arrayed in a two-dimensional grid, and a second structure that is stacked on the first structure, and has a second substrate, and a logic circuit and a non-volatile memory that are formed in the second substrate, in which a first protective film having a property of inhibiting entrance of hydrogen is formed on an end surface of a storage element included in the non-volatile memory which end surface is on a side facing the first structure, and a second protective film having the property of inhibiting entrance of hydrogen is formed on a side surface of the storage element.

Abstract: Provided are a display device and an electronic apparatus capable of improving the reliability of a light emission state of a pixel. A display device includes: a plurality of sub-pixels; a plurality of light emitting elements including an anode electrode, an organic layer, and a first cathode electrode, the anode electrode, the organic layer, and the first cathode electrode being separated into each of the plurality of sub-pixels; an element protective layer covering the first cathode electrode; a second cathode electrode provided on the element protective layer; and a connection portion that electrically connects the second cathode electrode and the first cathode electrode, in which the connection portion is formed along a side wall of the element protective layer.

Abstract: A solid-state image pickup apparatus includes: a first structure having a first substrate, and a pixel region including a plurality of pixels which is formed in the first substrate, outputs pixel signals according to amounts of electric charges generated by photoelectric conversion, and is arrayed in a two-dimensional grid, and a second structure that is stacked on the first structure, and has a second substrate, and a logic circuit and a non-volatile memory that are formed in the second substrate, in which a first protective film having a property of inhibiting entrance of hydrogen is formed on an end surface of a storage element included in the non-volatile memory which end surface is on a side facing the first structure, and a second protective film having the property of inhibiting entrance of hydrogen is formed on a side surface of the storage element.

Abstract: To provide a semiconductor device having a structure suitable for higher integration. This semiconductor device serving as an embodiment of the present disclosure includes: a storage element; a first contact that is electrically coupled to this storage element; a second contact that is positioned on an opposite side to the first contact in a first direction; a protective film that surrounds the storage element in a first plane orthogonal to the first direction; and a first hydrogen block layer that surrounds the protective film in the first plane. The second contact is electrically coupled to the storage element.

Abstract: The present technology relates to a semiconductor device, a manufacturing method, and a solid-state imaging device which are capable of suppressing a decrease in bonding strength and preventing a poor electrical connection or peeling when two substrates are bonded to each other. Provided is a semiconductor device, including: a first substrate including a first electrode including a metal; and a second substrate bonded to the first substrate and including a second electrode including a metal. An acute-angled concavo-convex portion is formed on a side surface of a groove in which the first electrode is formed and a side surface of a groove in which the second electrode metal-bonded to the first electrode is formed. The present technology can be, for example, applied to a solid-state imaging device such as a CMOS image sensor.

Abstract: The present technology relates to a semiconductor device, a manufacturing method, and a solid-state imaging device which are capable of suppressing a decrease in bonding strength and preventing a poor electrical connection or peeling when two substrates are bonded to each other. Provided is a semiconductor device, including: a first substrate including a first electrode including a metal; and a second substrate bonded to the first substrate and including a second electrode including a metal. An acute-angled concavo-convex portion is formed on a side surface of a groove in which the first electrode is formed and a side surface of a groove in which the second electrode metal-bonded to the first electrode is formed. The present technology can be, for example, applied to a solid-state imaging device such as a CMOS image sensor.

Abstract: A solid-state imaging device has: an imaging region in which a plurality of pixels each having a photoelectric conversion element are arranged, and a color filter. The color filter includes: filter components of a first color (2G), filter components of a second color (2R) formed by self-alignment and each being surrounded by the filter components of the first color (2G), and filter components of a third color (2B) formed by self-alignment and each being surrounded by the filter components of the first color (2G).

Abstract: A method for producing a solid-state imaging device includes steps of: forming transfer electrodes on a substrate having a plurality of light-sensing portions through a gate insulating layer so that the light-sensing portions are exposed; forming a planarized insulating layer on the substrate to cover the transfer electrodes formed on the substrate; forming openings in the planarized insulating layer so that each of the transfer electrodes is partly exposed out of the planarized insulating layer at a predetermined position; forming a wiring material layer so that the openings are filled with the wiring material layer; forming a resist layer on the wiring material layer; exposing and developing the resist layer so that only the resist layer in a predetermined area covering the openings is left; and patterning the wiring material layer using the exposed and developed resist layer to form connection wirings connected to the transfer electrodes by the openings.

Abstract: A solid-state imaging device has: an imaging region in which a plurality of pixels each having a photoelectric conversion element are arranged, and a color filter. The color filter includes: filter components of a first color (2G), filter components of a second color (2R) formed by self-alignment and each being surrounded by the filter components of the first color (2G), and filter components of a third color (2B) formed by self-alignment and each being surrounded by the filter components of the first color (2G).

Abstract: A method for producing a solid-state imaging device includes steps of: forming transfer electrodes on a substrate having a plurality of light-sensing portions through a gate insulating layer so that the light-sensing portions are exposed; forming a planarized insulating layer on the substrate to cover the transfer electrodes formed on the substrate; forming openings in the planarized insulating layer so that each of the transfer electrodes is partly exposed out of the planarized insulating layer at a predetermined position; forming a wiring material layer so that the openings are filled with the wiring material layer; forming a resist layer on the wiring material layer; exposing and developing the resist layer so that only the resist layer in a predetermined area covering the openings is left; and patterning the wiring material layer using the exposed and developed resist layer to form connection wirings connected to the transfer electrodes by the openings.

Abstract: A method of fabricating a semiconductor device, which is capable of effectively forming high reliability contacts in a plurality of regions to be contacted which are formed at different depths. The method includes the steps of: forming an etching stopper layer on an insulating layer covering a plurality of the regions to be contacted and having a stepped shape; selectively forming, in a lower height area of the insulating layer having the stepped shape, a conductive plug layer connected to a deeper region to be contacted which is formed under the lower height area of the insulating layer; forming a planarization layer on the lower height area of the insulating layer, followed by planarization over the entire surface; and selectively forming contact holes reaching the plug layer and other shallower regions to be contacted, simultaneously.

Abstract: A thin film transistor in which a device active layer is formed on an insulation film, in which an interface state density present at the interface between the active layer and the insulation film is set to less than 1.times.10.sup.11 /cm.sup.2. The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.

Abstract: A thin film transistor in which a device active layer is formed on an insulation film, in which an interface state density present at the interface between the active layer and the insulation film is set to less than 1.times.10.sup.11 /cm.sup.2. The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.

Abstract: A thin film transistor in which a device active layer is formed on an insulation film. In which an interface state density present at the interface between the active layer and the insulation film is set to less than 1.times.10.sup.11 /cm.sup.2. The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.