Patents by Inventor Tadayuki Kimura

Tadayuki Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200035643
    Abstract: The present technology relates to a semiconductor device, a manufacturing method, and a solid-state imaging device which are capable of suppressing a decrease in bonding strength and preventing a poor electrical connection or peeling when two substrates are bonded to each other. Provided is a semiconductor device, including: a first substrate including a first electrode including a metal; and a second substrate bonded to the first substrate and including a second electrode including a metal. An acute-angled concavo-convex portion is formed on a side surface of a groove in which the first electrode is formed and a side surface of a groove in which the second electrode metal-bonded to the first electrode is formed. The present technology can be, for example, applied to a solid-state imaging device such as a CMOS image sensor.
    Type: Application
    Filed: October 10, 2017
    Publication date: January 30, 2020
    Inventors: AKIKO HIRATA, TADAYUKI KIMURA, YASUFUMI MIYOSHI, KATSUNORI HIRAMATSU
  • Patent number: 10377312
    Abstract: Provided is an image display mirror that includes a half mirror and an image display apparatus, reduces an influence of a reflected image provided by the half mirror, and is excellent in visibility of an image displayed on the image display apparatus. The image display mirror for a vehicle includes a first polarizing plate, a half mirror, and an image display apparatus in the stated order from a viewer side. In one embodiment, the first polarizing plate includes a polarizer, and the direction of the polarizer of the first polarizing plate is set so that the transmittance of light output from the image display apparatus that is transmitted through the first polarizing plate becomes maximum.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: August 13, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Katsunori Takada, Tadayuki Kameyama, Yoshitsugu Kitamura, Keisuke Kimura, Hiroki Kuramoto
  • Patent number: 8373786
    Abstract: A solid-state imaging device has: an imaging region in which a plurality of pixels each having a photoelectric conversion element are arranged, and a color filter. The color filter includes: filter components of a first color (2G), filter components of a second color (2R) formed by self-alignment and each being surrounded by the filter components of the first color (2G), and filter components of a third color (2B) formed by self-alignment and each being surrounded by the filter components of the first color (2G).
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: February 12, 2013
    Assignee: Sony Corporation
    Inventors: Yoichi Otsuka, Yoshiyuki Enomoto, Kazunori Nagahata, Tadayuki Kimura, Toshihiko Hayashi, Kenichi Aoyagi, Kiyotaka Tabuchi, Iwao Sugiura, Kensaku Maeda
  • Patent number: 7977140
    Abstract: A method for producing a solid-state imaging device includes steps of: forming transfer electrodes on a substrate having a plurality of light-sensing portions through a gate insulating layer so that the light-sensing portions are exposed; forming a planarized insulating layer on the substrate to cover the transfer electrodes formed on the substrate; forming openings in the planarized insulating layer so that each of the transfer electrodes is partly exposed out of the planarized insulating layer at a predetermined position; forming a wiring material layer so that the openings are filled with the wiring material layer; forming a resist layer on the wiring material layer; exposing and developing the resist layer so that only the resist layer in a predetermined area covering the openings is left; and patterning the wiring material layer using the exposed and developed resist layer to form connection wirings connected to the transfer electrodes by the openings.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: July 12, 2011
    Assignee: Sony Corporation
    Inventors: Takeshi Takeda, Yukihiro Ando, Masaki Okamoto, Masayuki Okada, Kaori Takimoto, Katsuhisa Kugimiya, Tadayuki Kimura
  • Publication number: 20090303359
    Abstract: A solid-state imaging device has: an imaging region in which a plurality of pixels each having a photoelectric conversion element are arranged, and a color filter. The color filter includes: filter components of a first color (2G), filter components of a second color (2R) formed by self-alignment and each being surrounded by the filter components of the first color (2G), and filter components of a third color (2B) formed by self-alignment and each being surrounded by the filter components of the first color (2G).
    Type: Application
    Filed: May 1, 2009
    Publication date: December 10, 2009
    Applicant: Sony Corporation
    Inventors: Yoichi OTSUKA, Yoshiyuki ENOMOTO, Kazunori NAGAHATA, Tadayuki KIMURA, Toshihiko HAYASHI, Kenichi AOYAGI, Kiyotaka TABUCHI, Iwao SUGIURA, Kensaku MAEDA
  • Publication number: 20090263929
    Abstract: A method for producing a solid-state imaging device includes steps of: forming transfer electrodes on a substrate having a plurality of light-sensing portions through a gate insulating layer so that the light-sensing portions are exposed; forming a planarized insulating layer on the substrate to cover the transfer electrodes formed on the substrate; forming openings in the planarized insulating layer so that each of the transfer electrodes is partly exposed out of the planarized insulating layer at a predetermined position; forming a wiring material layer so that the openings are filled with the wiring material layer; forming a resist layer on the wiring material layer; exposing and developing the resist layer so that only the resist layer in a predetermined area covering the openings is left; and patterning the wiring material layer using the exposed and developed resist layer to form connection wirings connected to the transfer electrodes by the openings.
    Type: Application
    Filed: March 23, 2009
    Publication date: October 22, 2009
    Applicant: Sony Corporation
    Inventors: Takeshi Takeda, Yukihiro Ando, Masaki Okamoto, Masayuki Okada, Kaori Takimoto, Katsuhisa Kugimiya, Tadayuki Kimura
  • Patent number: 5869392
    Abstract: A method of fabricating a semiconductor device, which is capable of effectively forming high reliability contacts in a plurality of regions to be contacted which are formed at different depths. The method includes the steps of: forming an etching stopper layer on an insulating layer covering a plurality of the regions to be contacted and having a stepped shape; selectively forming, in a lower height area of the insulating layer having the stepped shape, a conductive plug layer connected to a deeper region to be contacted which is formed under the lower height area of the insulating layer; forming a planarization layer on the lower height area of the insulating layer, followed by planarization over the entire surface; and selectively forming contact holes reaching the plug layer and other shallower regions to be contacted, simultaneously.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: February 9, 1999
    Assignee: Sony Corporation
    Inventor: Tadayuki Kimura
  • Patent number: 5518939
    Abstract: A thin film transistor in which a device active layer is formed on an insulation film, in which an interface state density present at the interface between the active layer and the insulation film is set to less than 1.times.10.sup.11 /cm.sup.2. The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.
    Type: Grant
    Filed: February 15, 1995
    Date of Patent: May 21, 1996
    Assignee: Sony Corporation
    Inventors: Michio Negishi, Ihachi Naiki, Masayoshi Sasaki, Tadayuki Kimura
  • Patent number: 5506435
    Abstract: A thin film transistor in which a device active layer is formed on an insulation film, in which an interface state density present at the interface between the active layer and the insulation film is set to less than 1.times.10.sup.11 /cm.sup.2. The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.
    Type: Grant
    Filed: March 29, 1995
    Date of Patent: April 9, 1996
    Assignee: Sony Corporation
    Inventors: Michio Negishi, Ihachi Naiki, Masayoshi Sasaki, Tadayuki Kimura
  • Patent number: 5498557
    Abstract: A thin film transistor in which a device active layer is formed on an insulation film. In which an interface state density present at the interface between the active layer and the insulation film is set to less than 1.times.10.sup.11 /cm.sup.2. The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.
    Type: Grant
    Filed: April 14, 1994
    Date of Patent: March 12, 1996
    Assignee: Sony Corporation
    Inventors: Michio Negishi, Ihachi Naiki, Masayoshi Sasaki, Tadayuki Kimura