Abstract: A test pattern generation circuit outputs a test pattern during a clock phase adjustment period. A flip-flop circuit latches the test pattern at the fall of a shift clock and outputs it as a test pattern. A latch miss detection circuit outputs a latch miss detection signal indicating presence/absence of a latch miss generation according to the test pattern and a delay shift clock. A clock phase controller delays the shift clock according to the latch miss detection signal, thereby outputting a delay shift clock.

Abstract: A test pattern generation circuit (100) outputs a test pattern (TP) during a clock phase adjustment period. A flip-flop circuit (110) latches the test pattern (TP) at the fall of a shift clock (SCK) and outputs it as a test pattern (Tpa). A latch miss detection circuit (130) outputs a latch miss detection signal (LM) indicating presence/absence of a latch miss generation according to the test pattern (TPa) and a delay shift clock (DSCK). A clock phase control section (120) delays the shift clock (SCK) according to the latch miss detection signal (LM), thereby outputting a delay shift clock (DSCK).

Abstract: An AC plasma display device includes a pair of spaced apart first and second plates. The first plate bears electrodes each extending in a first direction, and the second plate bears paired first and second electrodes each extending in another direction perpendicular to the first direction. The paired first and second electrodes are divided into several groups. Further, the device includes first connecting lines connected to each other, each of which is associated with the first electrodes in one of the groups. Also provided are second connecting lines connected to each other, each of which is associated with the second electrodes in one of the groups. In addition, the device includes first pulse generators, each of which is associated with one of the first connecting lines and second pulse generators, each of which is associated with one of the second connecting lines.

Abstract: The display device of the present invention is provided with a means (8) for setting the writing pulse width of the attentional light-emitting sub-field wider than the normal writing pulse width at all the gray scale levels in the case where at least two continuous non-light-emitting sub-fields possibly exist before the attentional light-emitting sub-field at a certain gray scale level among all the gray scale levels specified on the basis of the number Z of sub-fields and the weighting of the sub-fields. According to the display device of the present invention, the discharge for writing can be stably executed without reducing the number of sub-fields in one field.

Abstract: An AC plasma display panel includes a plurality of parallel scan electrodes and a plurality of parallel sustain electrodes. Each of sustain electrodes is extended parallel to scan electrodes. Scan and sustain electrodes are positioned alternately so that each one of scan and sustain electrodes positions adjacent to and paired with the other of scan and sustain electrodes. Also, the panel includes a plurality of parallel data electrodes. The data electrodes extend substantially perpendicular to scan and sustain electrodes. Scan and sustain electrodes are applied with a certain current so that an electromagnetic noise generated in the electrodes can be cancelled by another.