Patents by Inventor Tadeu Marchese

Tadeu Marchese has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11599267
    Abstract: Example systems relate to system call acceleration. A system may include a processor and a non-transitory computer readable medium. The non-transitory computer readable medium may include instructions to cause the processor to run a plurality of benchmarks for a hardware configuration. The non-transitory computer readable medium may further include instructions to determine a benchmark matrix based on the plurality of benchmarks. The non-transitory computer readable medium may include instructions to determine an input/output (I/O) bandwidth ceiling for the hardware configuration based on the benchmark matrix. Additionally, the non-transitory computer readable medium may include instructions to determine a performance threshold of an I/O access parameter for the hardware configuration based on the bandwidth ceiling.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: March 7, 2023
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Tadeu Marchese, Raphael Gay, Taciano Perez
  • Patent number: 11294788
    Abstract: A program is executed on a first computer system and the execution of the program is monitored. A plurality of operation records are created based upon the monitoring, where each operation record is associated with an operation carried out during execution of the program. A first value of a cumulative performance indicator associated with the execution of the program on the first computer system is determined. For each operation record, a value of a performance indicator associated with carrying out the operation on a second computer system is predicted. For an operation record, the value of the performance indicator is predicted based on a performance model associated with carrying out operations on the second computer system. A second value of the cumulative performance indicator is determined, which is associated with execution of the program on the second computer system and is based on the predicted values of the performance indicator.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 5, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Taciano Perez, Tadeu Marchese, Pedro Henrique Garcez Monteiro, Raphael Gay
  • Patent number: 11216598
    Abstract: A method of securing a computer at a docking station, where the docking station includes a physical lock for selectively engaging with a locking interface of the computer to prevent removal of the computer from the docking station, the method includes: during a period of time in which the computer is registering a presence of an authenticated user at the computer, maintaining the physical lock of the docking station in an unlocked state disengaged from the locking interface of the computer; and when the computer is entering a locked state in response to a departure of the authenticated user from the computer, signaling the physical lock of the docking station to engage with the locking interface of the computer to prevent removal of the computer from the docking station.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: January 4, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mauricio Schramm, Tadeu Marchese
  • Publication number: 20210357118
    Abstract: Example systems relate to system call acceleration. A system may include a processor and a non-transitory computer readable medium. The non-transitory computer readable medium may include instructions to cause the processor to run a plurality of benchmarks for a hardware configuration. The non-transitory computer readable medium may further include instructions to determine a benchmark matrix based on the plurality of benchmarks. The non-transitory computer readable medium may include instructions to determine an input/output (I/O) bandwidth ceiling for the hardware configuration based on the benchmark matrix. Additionally, the non-transitory computer readable medium may include instructions to determine a performance threshold of an I/O access parameter for the hardware configuration based on the bandwidth ceiling.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 18, 2021
    Inventors: Tadeu Marchese, Raphael Gay, Taciano Perez
  • Publication number: 20210294721
    Abstract: A program is executed on a first computer system and the execution of the program is monitored. A plurality of operation records are created based upon the monitoring, where each operation record is associated with an operation carried out during execution of the program. A first value of a cumulative performance indicator associated with the execution of the program on the first computer system is determined. For each operation record, a value of a performance indicator associated with carrying out the operation on a second computer system is predicted. For an operation record, the value of the performance indicator is predicted based on a performance model associated with carrying out operations on the second computer system. A second value of the cumulative performance indicator is determined, which is associated with execution of the program on the second computer system and is based on the predicted values of the performance indicator.
    Type: Application
    Filed: July 20, 2017
    Publication date: September 23, 2021
    Inventors: Taciano Perez, Tadeu Marchese, Raphael Gay, Raphael Gay
  • Patent number: 11093136
    Abstract: Example systems relate to system call acceleration. A system may include a processor and a non-transitory computer readable medium. The non-transitory computer readable medium may include instructions to cause the processor to run a plurality of benchmarks for a hardware configuration. The non-transitory computer readable medium may further include instructions to determine a benchmark matrix based on the plurality of benchmarks. The non-transitory computer readable medium may include instructions to determine an input/output (I/O) bandwidth ceiling for the hardware configuration based on the benchmark matrix. Additionally, the non-transitory computer readable medium may include instructions to determine a performance threshold of an I/O access parameter for the hardware configuration based on the bandwidth ceiling.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: August 17, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Tadeu Marchese, Raphael Gay, Taciano Perez
  • Publication number: 20210157632
    Abstract: Examples of methods for controlling calls to a kernel by a computing device are described herein. In some examples of the methods, an amount of calls from a program to a scheduler function in a kernel space are determined in a user mode. In an example, a call from the program is intercepted in the user mode and the call is filtered in response to determining that the amount of calls satisfies a filtering criterion.
    Type: Application
    Filed: June 22, 2018
    Publication date: May 27, 2021
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Raphael Gay, Kirsten Olsen, Tadeu Marchese, Roberto Bender
  • Patent number: 10860246
    Abstract: Examples associated with persistent memory updating are described. One example includes receiving a first store instruction associated with a first page of memory in a persistent memory from an application. The first page is copied to a new page of the persistent memory. A virtual address space of the application is updated to a location of the new page in a read-write mode. The first store instruction is executed on the new page. A file mapping in the persistent memory is updated from a location of the first page to the location of the new page, and the virtual address space for the location of the new page is updated to a read-only mode.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: December 8, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Taciano Perez, Diego Medaglia, Tadeu Marchese
  • Publication number: 20200226300
    Abstract: A system may include a non-transitory computer readable medium and a processor. Instructions stored on the non-transitory computer readable medium may include instructions to transmit an identifier of a client device to a database. Instructions may further be executable to receive a code from the database indicating that the client device is allowed to boot. Further instructions may be executable by the processor to run an operating system of the client device in response to receiving the code from the database.
    Type: Application
    Filed: October 3, 2017
    Publication date: July 16, 2020
    Inventors: Tadeu Marchese, José Dirceu Gründler Ramos, Taciano Perez
  • Publication number: 20190370506
    Abstract: A method of securing a computer at a docking station, where the docking station includes a physical lock for selectively engaging with a locking interface of the computer to prevent removal of the computer from the docking station, the method includes: during a period of time in which the computer is registering a presence of an authenticated user at the computer, maintaining the physical lock of the docking station in an unlocked state disengaged from the locking interface of the computer; and when the computer is entering a locked state in response to a departure of the authenticated user from the computer, signaling the physical lock of the docking station to engage with the locking interface of the computer to prevent removal of the computer from the docking station.
    Type: Application
    Filed: September 12, 2016
    Publication date: December 5, 2019
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Mauricio Schramm, Tadeu Marchese
  • Publication number: 20190347003
    Abstract: Example systems relate to system call acceleration. A system may include a processor and a non-transitory computer readable medium. The non-transitory computer readable medium may include instructions to cause the processor to run a plurality of benchmarks for a hardware configuration. The non-transitory computer readable medium may further include instructions to determine a benchmark matrix based on the plurality of benchmarks. The non-transitory computer readable medium may include instructions to determine an input/output (I/O) bandwidth ceiling for the hardware configuration based on the benchmark matrix. Additionally, the non-transitory computer readable medium may include instructions to determine a performance threshold of an I/O access parameter for the hardware configuration based on the bandwidth ceiling.
    Type: Application
    Filed: February 1, 2017
    Publication date: November 14, 2019
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Tadeu Marchese, Raphael Gay, Taciano Perez
  • Publication number: 20190310796
    Abstract: Examples associated with persistent memory updating are described. One example includes receiving a first store instruction associated with a first page of memory in a persistent memory from an application. The first page is copied to a new page of the persistent memory. A virtual address space of the application is updated to a location of the new page in a read-write mode. The first store instruction is executed on the new page. A file mapping in the persistent memory is updated from a location of the first page to the location of the new page, and the virtual address space for the location of the new page is updated to a read-only mode.
    Type: Application
    Filed: December 21, 2016
    Publication date: October 10, 2019
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Taciano PEREZ, Diego MEDAGLIA, Tadeu MARCHESE
  • Publication number: 20180285575
    Abstract: Examples include a system comprising a processing resource and a memory resource. Examples include a cryptography engine arranged in-line with the processing resource and the memory resource. The cryptography engine is to selectively decrypt data during read accesses of the memory resource by the processing resource.
    Type: Application
    Filed: January 21, 2016
    Publication date: October 4, 2018
    Inventors: Tadeu Marchese, Christian Perone, Diego Medaglia, Wagston Staehler