Abstract: An adder-subtractor includes a jth device for each bit position j for computing a result for an expression .+-.a.sub.0 .+-.a.sub.1, where a.sub.0 and a.sub.1 are binary numbers. The jth device is from a group of devices, the group being defined by formulas using integer parameters k, p.sub.0, p.sub.1, t, x.sub.0, x.sub.1, y.sub.0, and y.sub.1, each of the parameters having a integer value that is 0 or 1. The jth device includes a line carrying an input a.sub.1j representing a jth digit of the a.sub.1 number. The jth device further includes a line carrying an input w.sub.1j =1-y.sub.1 when s.sub.1 =1-x.sub.1 and if a previous bit position of the a.sub.1 number is 1, and w.sub.1j =y.sub.1 when s.sub.1 =1-x.sub.1 and there is no 1 on previous bit position. A plurality of switches, between the lines, direct to the forward output F.sub.out a bit value, according to one of said formulas:F.sub.out =(1-p.sub.k)(s.sub.k .sym.x.sub.k)(w.sub.kj .sym.y.sub.k).sym.a.sub.kj .sym.tifp.sub.0 (s.sub.0 .sym.x.sub.0).sym.(1-p.