Patents by Inventor Tadhg Creedon
Tadhg Creedon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9158727Abstract: An exemplary method and system of addressing an integrated circuit within a daisy chain network. In the exemplary method, the address of the integrated circuit may be initialized to a predetermined initial address. The integrated circuit may receive a command that includes a type identifier and an address field. Based on the type identifier, the type of command may be determined. As a result of the determination, reading the address from the address field. The read address may be stored in a register. The address may be modified, and may be output. Upon receipt of the data or a command, the integrity of the data including data within the received command, may be confirmed by an error checking algorithm.Type: GrantFiled: April 30, 2010Date of Patent: October 13, 2015Assignee: ANALOG DEVICES, INC.Inventors: Jeremy Gorbold, James Gibbons, Tadhg Creedon, Katherine O'Riordan, John Reidy, John Morrissey
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Publication number: 20120150527Abstract: An emulation system (1) comprises a programming system (2) made up of a laptop computer (2(a)) and a central server (2(b)), an interrogation station (3), and a programmable storage peripheral device (4). The system (1) links with an existing disk storage peripheral device (10) to retrieve characterisation data, and upload it to the central server (2(b)). The laptop computer (2(a)) then retrieves the characterization data and then programs the programmable device (4) to emulate the full functionality of the pre-existing computer storage peripheral (10). The device (4) is programmed by the host computer (2) to fully replicate characteristics including electrical and timing characteristics and command responses. The programmable device (4) does not have a disk drive, the only storage components being solid state non-volatile memory components, in this embodiment flash memory and volatile components including DRAM. The flash components include mostly NAND flash, but also NOR flash.Type: ApplicationFiled: August 20, 2010Publication date: June 14, 2012Inventors: Tadhg Creedon, Vincent Gavin, Eugene McCabe
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Publication number: 20100280786Abstract: An exemplary method and system of addressing an integrated circuit within a daisy chain network. In the exemplary method, the address of the integrated circuit may be initialized to a predetermined initial address. The integrated circuit may receive a command that includes a type identifier and an address field. Based on the type identifier, the type of command may be determined. As a result of the determination, reading the address from the address field. The read address may be stored in a register. The address may be modified, and may be output. Upon receipt of the data or a command, the integrity of the data including data within the received command, may be confirmed by an error checking algorithm.Type: ApplicationFiled: April 30, 2010Publication date: November 4, 2010Applicant: ANALOG DEVICES, INC.Inventors: Jeremy GORBOLD, James GIBBONS, Tadhg CREEDON, Katherine O'RIORDAN, John REIDY, John MORRISSEY
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Patent number: 7656330Abstract: Automatic range shifting for an analog to digital converter (ADC) includes combining an external analog input and a DAC output to provide an input to the ADC, detecting whether the range of the output of the ADC is above a predetermined upper range limit or below a predetermined lower range limit, and generating an adjustment code to increase the DAC output if the ADC output is above the upper range limit and to decrease the DAC output if the ADC output is below the lower range limit for decreasing the ADC input when the ADC output is above the upper limit and to increase the ADC input when the ADC output is below the lower limit to keep the ADC input within the ADC range.Type: GrantFiled: May 22, 2008Date of Patent: February 2, 2010Assignee: Analog Devices, Inc.Inventors: John O'Dowd, Kevin Jennings, Tadhg Creedon
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Publication number: 20080291067Abstract: Automatic range shifting for an analog to digital converter (ADC) includes combining an external analog input and a DAC output to provide an input to the ADC, detecting whether the range of the output of the ADC is above a predetermined upper range limit or below a predetermined lower range limit, and generating an adjustment code to increase the DAC output if the ADC output is above the upper range limit and to decrease the DAC output if the ADC output is below the lower range limit for decreasing the ADC input when the ADC output is above the upper limit and to increase the ADC input when the ADC output is below the lower limit to keep the ADC input within the ADC range.Type: ApplicationFiled: May 22, 2008Publication date: November 27, 2008Inventors: John O'Dowd, Kevin Jennings, Tadhg Creedon
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System for detection of asynchronous packet rates and maintenance of maximum theoretical packet rate
Patent number: 6882661Abstract: A system transfers a data stream including data packets separated by non-packet words from a first clock domain to a second clock domain. It includes an elasticity buffer into which the data stream is written in a cyclic sequence under the control of the clock frequency in the first clock domain and from which the data stream is read out in a cyclic sequence under the control of the clock frequency in the second domain. The two sequences are monitored to provide an anticipatory signal indicating that the reading sequence approaches proximity to the writing sequence. A non-packet word is inserted into the data stream in the first domain. In the second clock domain the existence of the inserted non-packet word is detected and the buffer is caused to advance the reading cycle thereby to discard the said inserted non-packet word.Type: GrantFiled: September 14, 2000Date of Patent: April 19, 2005Assignee: 3Com CorporationInventors: Tadhg Creedon, Denise De Paor, Fergus Casey -
Patent number: 6877145Abstract: A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.Type: GrantFiled: August 2, 2001Date of Patent: April 5, 2005Assignee: 3Com CorporationInventors: Sean Boylan, Derek Coburn, Tadhg Creedon, Denise De Paor, Vincent Gavin, Kevin J Hyland, Suzanne M Hughes, Kevin Jennings, Mike Lardner, Brendan Walsh
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Patent number: 6718411Abstract: An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.Type: GrantFiled: June 29, 2001Date of Patent: April 6, 2004Assignee: 3Com CorporationInventors: Tadhg Creedon, Vincent Gavin, Denise de Paor, Kevin J Hyland, Kevin Jennings, Derek Coburn, Mike Lardner, Suzanne M Hughes, Sean Boylan, Brendan Walsh
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Patent number: 6684258Abstract: A stackable network unit which can form a ring with other units has a master mode in which it can place packets on the ring, so that they can be ultimately forwarded from other units, and a repeat mode in which it can make a request for transfer of mastership of the ring, inserting bits in a header of an arbitration packet. If a master unit has completed the transmission of a packet and, preferably, after the required inter-packet gap has elapsed, it has not yet received an arbitration header to permit the making of an arbitration decision it can transmit a subsequent packet. The header information of this packet indicates to the other units that this subsequent packet is part of a burst of packets and the other units should not set requests in the header of this packet because this packet would not be used for arbitration.Type: GrantFiled: April 12, 2000Date of Patent: January 27, 2004Assignee: 3Com CorporationInventors: Vincent Gavin, Una Quinlan, Denise De Paor, Tadhg Creedon, Nicholas M Stapleton
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Patent number: 6587389Abstract: A method and apparatus for refresh command operations on an SDRAM that avoids use of refresh commands requiring all banks of the SDRAM to be idle. Burst operation establishes command sequences that include Nop command intervals. Some of these Nop intervals are used to perform operations on a bank other than the one under access for the burst that provide a refresh. ACTIVE followed by PRECHARGE commands are inserted into the command intervals addressed to a refresh address. The refresh addresses are generated externally of the SDRAM and provided to a multiplexer that sequences them with the data addresses. A secondary timer checks that required refresh has occurred and prioritizes the refresh addresses over data addresses in the multiplexer in the event that a refresh has not been completed shortly before a maximum refresh interval.Type: GrantFiled: October 30, 2001Date of Patent: July 1, 2003Assignee: 3Com CorporationInventors: Denise De Paor, Tadhg Creedon
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Publication number: 20030101331Abstract: A view-based design technique for an ASIC includes selecting a particular multiple level hierarchy and for each level in the hierarchy creating a hardware description language file which declares the relevant signals and module instantiations.Type: ApplicationFiled: December 6, 2001Publication date: May 29, 2003Inventors: Sean T. Boylan, Vincent G. Gavin, Kevin Jennings, Mike Lardner, Tadhg Creedon, Brendan G. Boesen
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Publication number: 20030081483Abstract: Burst operation establishes command sequences that include Nop command intervals Some of these Nop intervals are used to perform operations on a bank other than the one under access for the burst that provide a refresh. ACTIVE followed by PRECHARGE commands are inserted into the command intervals addressed to a refresh address The refresh addresses are generated externally of the SDRAM and provided to a multiplexer that sequences them with the data addresses.Type: ApplicationFiled: October 30, 2001Publication date: May 1, 2003Inventors: Denise De Paor, Tadhg Creedon
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Patent number: 6552590Abstract: A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of the higher frequency block and can be achieved without elastic buffers and/or synchronizers.Type: GrantFiled: June 13, 2001Date of Patent: April 22, 2003Assignee: 3Com CorporationInventors: Susan M Pratt, Vincent Gavin, Tadhg Creedon, Suzanne M Hughes, Mike Lardner, Padraic O'Reilly
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Publication number: 20030018738Abstract: A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.Type: ApplicationFiled: August 2, 2001Publication date: January 23, 2003Inventors: Sean Boylan, Derek Coburn, Tadhg Creedon, Denise C. De Paor, Vincent G. Gavin, Kevin J. Hyland, Suzanne Hughes, Kevin Jennings, Mike Lardner, Brendan Walsh
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Publication number: 20020184453Abstract: A data bus system in which a read or write transaction includes an identification of the initiator of the transaction and optionally an identification of the transaction as a number in a cyclic progression and optionally a request for an acknowledgement.Type: ApplicationFiled: June 29, 2001Publication date: December 5, 2002Inventors: Suzanne M. Hughes, Tadhg Creedon, Denise De Paor, Vincent Gavin, Kevin J. Hyland, Kevin Jennings, Mike Lardner, Derek Coburn
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Publication number: 20020184419Abstract: An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widthsType: ApplicationFiled: June 29, 2001Publication date: December 5, 2002Inventors: Tadhg Creedon, Vincent Gavin, Denise De Paor, Kevin J. Hyland, Kevin Jennings, Derek Coburn, Mike Lardner, Suzanne M. Hughes, Sean Boylan, Brendan Walsh
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Patent number: 6486450Abstract: An application specific integrated circuit includes a multiplicity of operative circuit blocks. Disposed in at least one of the blocks is a multiplicity of selectively operative heater modules for providing localised heating within the block. The heater modules may comprise cyclic redundancy code generators each coupled to respond to a system clock, and each heater module may include a system clock divider providing a multiplicity of differently divided clock signals and means for selecting a clock signal for use by the module. The invention is useful in design variable testing to produce variation with temperature of the frequency of an intermittent timing error.Type: GrantFiled: September 14, 2000Date of Patent: November 26, 2002Assignee: 3Com CorporationInventors: Una Quinlan, Vincent Gavin, Tadhg Creedon
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Publication number: 20020140457Abstract: A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of the higher frequency block and can be achieved without elastic buffers and/or synchronisersType: ApplicationFiled: June 13, 2001Publication date: October 3, 2002Inventors: Susan M. Pratt, Vincent Gavin, Tadhg Creedon, Suzanne M. Hughes, Mike Lardner, Padraic O'Reilly
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Publication number: 20020118178Abstract: A key pad scanner having a shift register driving the column lines and a parallel-in serial-out register coupled to the row lines of the keypad Each scanning cycle comprises a multiplicity of sub-cycles in of which serial data signals for the shift register identify a single respective one of the column lines The scanner may be coupled to an ASIC entirely by serial data signalsType: ApplicationFiled: May 21, 2001Publication date: August 29, 2002Inventors: Mairtin P. O'Conghaile, Tadhg Creedon
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Patent number: 6430192Abstract: A method of operating a repeater for a packet-based data transmission system wherein the repeater has a receiving port associated with a buffer whereby packets received at the port are temporarily stored before they are onwardly transmitted and wherein the repeater performs a contention resolution process such that if an attempted onward transmission of a packet is prevented by virtue of contention with a prior or an existing transmission, a subsequent attempt at transmission of that packet is delayed for a time which is likely to be substantially greater than a selected minimum time. The method includes examining a received packet to determine whether the packet is a multi-media packet, and giving the packet a higher priority in the contention resolution process such that if the packet is not transmitted onwardly owing to contention with a prior transmission, a fresh attempt at transmission of the packet is made on the expiry of the selected minimum time.Type: GrantFiled: January 14, 1999Date of Patent: August 6, 2002Assignee: 3COM TechnologiesInventors: Tadhg Creedon, David J. Law, Terence D. Lockyer, Nigel Horspool