Patents by Inventor Tae-Byung Hwang

Tae-Byung Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method of making the same
    Patent number: 6326669
    Abstract: A semiconductor device and a method of making the semiconductor device are disclosed. The semiconductor device includes a substrate having at least one gate electrode, the gate electrode having lateral walls and edges. Spacers are formed on the lateral walls of the gate electrode, and active areas are formed inside the substrate at the edges of the gate electrode. A DRAM cell forming part is disposed on a portion of the substrate, and includes at least one gate electrode and an active area, and a logic forming part is disposed on another portion of the substrate, and includes at least one gate electrode and an active area. The device further includes a silicide blocking layer disposed at the active area of the DRAM cell forming part, and a silicide layer formed on at least one gate electrode of the DRAM cell forming part, and on a gate electrode and the active area of the logic forming part.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: December 4, 2001
    Assignee: Samsung Electronics Co., LTD
    Inventors: Tae-Byung Hwang, Duck-Hyung Lee
  • Method of preventing misalignment of selective silicide layer in the manufacture of a DRAM device and the DRAM device formed thereby
    Patent number: 6162675
    Abstract: A semiconductor device and a method of making the semiconductor device are disclosed. The semiconductor device includes a substrate having at least one gate electrode, the gate electrode having lateral walls and edges. Spacers are formed on the lateral walls of the gate electrode, and active areas are formed inside the substrate at the edges of the gate electrode. A DRAM cell forming part is disposed on a portion of the substrate, and includes at least one gate electrode and an active area, and a logic forming part is disposed on another portion of the substrate, and includes at least one gate electrode and an active area. The device further includes a silicide blocking layer disposed at the active area of the DRAM cell forming part, and a silicide layer formed on at least one gate electrode of the DRAM cell forming part, and on a gate electrode and the active area of the logic forming part.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: December 19, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Byung Hwang, Duck-Hyung Lee