Abstract: A vertically structured transistor and method for manufacturing the same achieves a highly integrated semiconductor device. A pillar is vertically formed on a semiconductor substrate and forms a channel region of the transistor. A gate electrode is formed in a self-alignment fashion so as to surround the sides of the pillar with a gate insulating film imposed therebetween. A source region and a drain region are formed in a lower portion and an upper portion of the pillar, respectively. The area occupied by a transistor according to the present invention is remarkably reduced.

Abstract: A vertically structured transistor and method for manufacturing the same achieves a highly integrated semiconductor device. A pillar is vertically formed on a semiconductor substrate and forms a channel region of the transistor. A gate electrode is formed in a self-alignment fashion so as to surround the sides of the pillar with a gate insulating film imposed therebetween. A source region and a drain region are formed in a lower portion and an upper portion of the pillar, respectively. The area occupied by a transistor according to the present invention is remarkably reduced.

Abstract: A method for manufacturing an electrode, e.g., a gate electrode of a MOS transistor, and an electrode and MOS transistor manufactured in accordance with this method. The method includes the steps of forming a first diffusion preventing layer on an underlying layer, forming a mask pattern having an opening on the first diffusion preventing layer, forming a metal layer on a portion of the first diffusion preventing layer exposed by the opening in the mask pattern, forming a metal layer on the exposed portion of the first diffusion preventing layer, forming a second diffusion preventing layer on the resultant structure, etching back the second diffusion preventing layer to leave a remaining portion thereof on the metal layer, removing the mask pattern, and forming a third diffusion preventing layer on exposed portions of the remaining portion of the second diffusion preventing layer, exposed sidewalls of the metal layer, and exposed portions of the first diffusion preventing layer.