Abstract: A quantum dot, a quantum dot composite, a composition for preparing a quantum dot composite, a display panel including the quantum dot composite, and an electronic device including the display panel, wherein the quantum dot includes a core including a semiconductor nanocrystal including indium and phosphorus, a shell disposed on the core and including a semiconductor nanocrystal, and a compound represented by Chemical Formula 1 and a compound represented by Chemical Formula 2, both of which are present on the surface of the shell:

Abstract: A method and an apparatus for real-time analysis of the district heating network is disclosed. According to an embodiment of the present disclosure, a method for analyzing a district heating network including pipes and fluids inside the pipes includes receiving, by a processor, pipe data representing a structure of the pipes; receiving, by the processor, input data on at least one of the physical state of the district heating network and the flow of fluids; calculating, by the processor, data for at least one of the physical state of the district heating network or the flow of fluids using the pipe data and the input data.

Abstract: A robot system for adjusting a machining load depending on tool wear includes a robot that is coupled to a machining unit, moves the machining unit to change a position of a tool with respect to a machining target, and has a plurality of joints. The robot system further includes a support that supports the machining target and moves the machining target to change a position of the machining target with respect to the tool, a sensor unit that is provided on the machining unit and measures an amount of current supplied to a machining motor which operates the tool or an operation force of the tool, and a controller that receives a measurement signal from the sensor unit and transmits a control signal to the robot and the support.

Abstract: An electrode includes an electrode active material, wherein the electrode active material layer includes an electrode active material, polyvinylidene fluoride, and a conductive agent, wherein the conductive agent includes a carbon nanotube structure in which 2 to 5,000 single-walled carbon nanotube units are bonded to each other, and the carbon nanotube structure is included in an amount of 0.01 wt % to 0.5 wt % in the electrode active material layer. A secondary battery including the same, and a method of preparing the electrode are also provided.

Abstract: A semiconductor device and an electronic system including the same are disclosed. The semiconductor device may include a substrate including a cell array region and a connection region, the cell array region comprising a center region and an outer region; an electrode structure including electrodes and pads; vertical structures on the cell array region and penetrating the electrode structure; and a separation insulating pattern penetrating and dividing an upper electrode, which is one of the electrodes, into at least two portions arranged in a second direction crossing the first direction. The separation insulating pattern comprises a first portion and a second portion, the first portion is between at least some of the central vertical structures, and the second portion is spaced apart from the first portion such that, when viewed in the plan view, the second portion is between at least some of the peripheral vertical structure.

Abstract: A circuit board includes a top surface; a bottom surface; and a heat-dissipating portion, wherein the heat-dissipating portion extends from the top surface of the circuit board to the bottom surface of the circuit board, and a first surface of the heat-dissipating portion is exposed out of the top surface of the circuit board, and a second surface of the heat-dissipating portion is exposed out of the bottom surface of the circuit board.

Abstract: Disclosed herein are a method for manufacturing an electronic component embedding substrate and an electronic component embedding substrate. The method for manufacturing an electronic component embedding substrate includes: inserting an electronic component into a cavity formed in a core substrate; stacking a first insulating layer on one side of the core substrate into which the electronic component is inserted; performing surface treatment on the other side of the core substrate opposite to a direction in which the first insulating layer is stacked to improve a surface roughness of at least an exposed surface of the first insulating layer; and stacking a second insulating layer on the other side of the core substrate so as to be bonded to the exposed surface of the first insulating layer of which the surface roughness is improved. In addition, disclosed herein is the electronic component embedding substrate.

Abstract: Embodiments of the invention provide an electronic component-embedded substrate and a manufacturing method thereof. According to at least one embodiment, the electronic component-embedded substrate includes a cavity formed in a core substrate and including two or more embedding spaces which have a rectangular shape (when viewed on a plane) and are connected to each other by a connecting space, and two or more electronic components separately accommodated in the embedding spaces of the cavity, respectively. According to at least one embodiment, neighboring long sides of first and second embedding spaces are partially connected to each other by the connecting space, and one side (when viewed on the plane) forming a connecting width of the connecting space connecting the first and second embedding spaces to each other coincides with one short side of the first embedding space, and the other side (when viewed on the plane) coincides with the other short side of the second embedding space.

Abstract: Disclosed herein are a method for manufacturing an electronic component embedding substrate and an electronic component embedding substrate. The method for manufacturing an electronic component embedding substrate includes: inserting an electronic component into a cavity formed in a core substrate; stacking a first insulating layer on one side of the core substrate into which the electronic component is inserted; performing surface treatment on the other side of the core substrate opposite to a direction in which the first insulating layer is stacked to improve a surface roughness of at least an exposed surface of the first insulating layer; and stacking a second insulating layer on the other side of the core substrate so as to be bonded to the exposed surface of the first insulating layer of which the surface roughness is improved. In addition, disclosed herein is the electronic component embedding substrate.

Abstract: A method for fabricating a semiconductor package substrate, including: preparing a copper clad laminate and half etching a copper foil on a wire bonding pad side of the copper clad laminate; depositing a first etching resist on the opposite sides of the copper clad laminate; forming circuit patterns on the first etching resist, constructing circuits including a wire bonding pad and a ball pad after the model of the circuit patterns, and removing the first etching resist; applying a solder resist to the copper clad laminate in such a way to expose the wire bonding pad and the ball pad; and plating the wire bonding pad with gold and subjecting the ball pad to surface treatment.

Abstract: A printed circuit board for a package includes a first insulation layer, on one side of which an electronic component having a plurality of electrical contacts is mounted; a plurality of first bond pads formed on the other side of the first insulation layer in predetermined intervals, which are electrically connected with the electrical contacts; a second insulation layer stacked on the other side of the first insulation layer, with those portions removed where the first bond pads are formed; and a second bond pad, which is formed on a surface of the second insulation layer in correspondence with positions between the plurality of the first bond pads, and which is electrically connected with the electrical contacts. The bond pads can be implemented in two layers, as opposed to the case of forming the bond pads in one layer, in a predetermined area of a printed circuit board.

Abstract: A printed circuit board and a method of manufacturing the same are disclosed. The method of manufacturing a printed circuit board including a connecting layer configured to which is configured to electrically connect both sides of an insulator, and a pad part, electrically connect both sides of an insulator, and a pad part formed in one side of the insulator to be directly in contact with the connecting layer, includes: forming a seed layer part on one side of the insulator, a portion of the seed layer part being bulged, forming a via hole by processing the other side of the insulator, corresponding to the bulged portion of the seed layer part, forming the connecting layer inside the via hole, and forming a plating layer, corresponding to the pad part, on the seed layer part. A pattern having a finer pitch, maintaining a VOP structure, can be formed and a lower side of a substrate is not penetrated through when a via hole is processed.

Abstract: A method for fabricating a semiconductor package substrate, including: preparing a copper clad laminate and half etching a copper foil on a wire bonding pad side of the copper clad laminate; depositing a first etching resist on the opposite sides of the copper clad laminate; forming circuit patterns on the first etching resist, constructing circuits including a wire bonding pad and a ball pad after the model of the circuit patterns, and removing the first etching resist; applying a solder resist to the copper clad laminate in such a way to expose the wire bonding pad and the ball pad; and plating the wire bonding pad with gold and subjecting the ball pad to surface treatment.

Abstract: Disclosed herein is a Ball Grid Array (BGA) package board. The BGA package board includes a first external layer on which a pattern comprising a circuit pattern and a wire bonding pad pattern is formed, a second external layer on which a pattern comprising a circuit pattern and a solder ball pad pattern is formed, an insulating layer formed between the first and second external layers, a first outer via hole to electrically connect the first and second external layers to each other, and a solder resist layer formed on each of the first and second external layers, with portions of the solder resist layer corresponding to the wire bonding pad pattern and the solder ball pad pattern being opened. The solder ball pad pattern is thinner than the circuit pattern of the second external layer.

Abstract: Disclosed herein are a semiconductor package substrate and a method for fabricating the same. In the semiconductor package substrate, the circuit layer of the wire bonding pad side differs in thickness from that of the ball pad side to which a half etching process is applied. In addition, a connection through hole is constructed to provide an electrical connection between the plating lead lines on the wire bonding pad side and the ball pad side, thereby preventing electrical disconnection when the plating lead line of the wire bonding pad side is cut.

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. The method of manufacturing a printed circuit board including a via, which is configured to electrically connect both sides of an insulator, and a pad part, which is formed in one side of the insulator to be directly in contact with the via, can include forming a seed layer part on one side of the insulator, a portion of the seed layer part being bulged, forming a via hole by processing the other side of the insulator, corresponding to the bulged portion of the seed layer part, forming the via inside the via hole, and forming a plating layer, corresponding to the pad part, on the seed layer part. With the present invention, it is possible to form a pattern having a finer pitch, maintaining a VOP structure and to prevent a lower side of a substrate from being penetrated through when a via hole is processed.

Abstract: A printed circuit board is disclosed. The printed circuit board, which may include an insulation layer, a first metal pad formed on the insulation layer, a second metal pad electrically coupled with the first metal pad and having an ionization tendency lower than that of the first metal pad, and a sacrificial electrode electrically coupled with the second metal pad to prevent corrosion in the first metal pad, can be utilized to prevent excessive etching that may otherwise occur due to galvanic corrosion between metal pads of different ionization tendencies.

Abstract: Disclosed herein is a Ball Grid Array (BGA) package board. The BGA package board includes a first external layer on which a pattern comprising a circuit pattern and a wire bonding pad pattern is formed, a second external layer on which a pattern comprising a circuit pattern and a solder ball pad pattern is formed, an insulating layer formed between the first and second external layers, a first outer via hole to electrically connect the first and second external layers to each other, and a solder resist layer formed on each of the first and second external layers, with portions of the solder resist layer corresponding to the wire bonding pad pattern and the solder ball pad pattern being opened. The solder ball pad pattern is thinner than the circuit pattern of the second external layer.

Abstract: In the BGA package and its manufacturing method, a bonding pad is etched from the exposed surface to a part of the insulation layer-coated region so as to form a solder contact side having a dish configuration, which is planar at a bottom center and slanted at a periphery. With this bent structure of the dish configuration, the bonding pad provides an increased bonding area for the solder, so that the BGA package substrate is enhanced in reliability.

Abstract: Disclosed herein is a Ball Grid Array (BGA) package board. The BGA package board includes a first external layer on which a pattern comprising a circuit pattern and a wire bonding pad pattern is formed, a second external layer on which a pattern comprising a circuit pattern and a solder ball pad pattern is formed, an insulating layer formed between the first and second external layers, a first outer via hole to electrically connect the first and second external layers to each other, and a solder resist layer formed on each of the first and second external layers, with portions of the solder resist layer corresponding to the wire bonding pad pattern and the solder ball pad pattern being opened. The solder ball pad pattern is thinner than the circuit pattern of the second external layer.