Abstract: In a video cassette recorder incorporating two interconnected microcomputers for its control, an automatic watchdog method sends from a first microcomputer a request command for watchdog data to a second microcomputer periodically. Upon receiving the watchdog data request command, the second microcomputer, if operating normally, is forced to respond to the watchdog data generated in a predetermined manner. Accordingly, when the first microcomputer receives the watchdog data generated not in the predetermined manner, or does not receive the watchdog data at all, it recognizes that the second microcomputer is in an errant state. When the first microcomputer detects such an abnormality in the second microcomputer, it reinitializes the second microcomputer through a reset port thereof.

Abstract: A novel apparatus, for use with a microcomputer, for detecting an erroneous input clock signal and/or an input supply voltage to the microcomputer and providing a reliable reset signal thereto, comprises a converter for converting a differential signal representing the phase difference between the input clock signal and a feedback clock signal into a differential voltage and for generating a reference clock signal having a number of logic high and logic low states in response to the differential voltage, wherein the feedback clock signal represents a previously generated reference clock signal; a first comparator for comparing the differential voltage and the input supply voltage with first and second predetermined threshold values, respectively, to detect first and second error signals and for generating an error decision signal based on the first and the second error signals; a circuit, responsive to the error decision signal and a counting value state signal denoting a previously provided reset signal, for