Abstract: A printed circuit board and a method of manufacturing the same are disclosed. The method of manufacturing a printed circuit board including a connecting layer configured to which is configured to electrically connect both sides of an insulator, and a pad part, electrically connect both sides of an insulator, and a pad part formed in one side of the insulator to be directly in contact with the connecting layer, includes: forming a seed layer part on one side of the insulator, a portion of the seed layer part being bulged, forming a via hole by processing the other side of the insulator, corresponding to the bulged portion of the seed layer part, forming the connecting layer inside the via hole, and forming a plating layer, corresponding to the pad part, on the seed layer part. A pattern having a finer pitch, maintaining a VOP structure, can be formed and a lower side of a substrate is not penetrated through when a via hole is processed.

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. The method of manufacturing a printed circuit board including a via, which is configured to electrically connect both sides of an insulator, and a pad part, which is formed in one side of the insulator to be directly in contact with the via, can include forming a seed layer part on one side of the insulator, a portion of the seed layer part being bulged, forming a via hole by processing the other side of the insulator, corresponding to the bulged portion of the seed layer part, forming the via inside the via hole, and forming a plating layer, corresponding to the pad part, on the seed layer part. With the present invention, it is possible to form a pattern having a finer pitch, maintaining a VOP structure and to prevent a lower side of a substrate from being penetrated through when a via hole is processed.

Abstract: A package substrate of, for example, a BGA type or a CSP type, manufactured by carrying out an electrolytic Au plating process without using any plating lead line for formation of bond fingers and solder ball pads, and a method for manufacturing the package substrate.

Abstract: A package substrate of, for example, a BGA type or a CSP type, manufactured by carrying out an electrolytic Au plating process without using any plating lead line for formation of bond fingers and solder ball pads, and a method for manufacturing the package substrate.

Abstract: Disclosed is a package substrate for electrolytic leadless plating, characterized in that a wire bonding pad onto which a semiconductor chip is mounted is subjected to electrolytic leadless Au plating, and a solder ball pad is subjected to OSP metal finishing or electroless Au plating without use of plating lead lines, upon preparation thereof. A method of manufacturing the package substrate is also disclosed.

Abstract: A package substrate of, for example, a BGA type or a CSP type, manufactured by carrying out an electrolytic Au plating process without using any plating lead line for formation of bond fingers and solder ball pads, and a method for manufacturing the package substrate.

Abstract: Disclosed is a package substrate for electrolytic leadless plating, characterized in that a wire bonding pad onto which a semiconductor chip is mounted is subjected to electrolytic leadless Au plating, and a solder ball pad is subjected to OSP metal finishing or electroless Au plating without use of plating lead lines, upon preparation thereof. A method of manufacturing the package substrate is also disclosed.

Abstract: A package substrate of, for example, a BGA type or a CSP type, manufactured by carrying out an electrolytic Au plating process without using any plating lead line for formation of bond fingers and solder ball pads, and a method for manufacturing the package substrate.