Patents by Inventor Tae-Gyoung Kang
Tae-Gyoung Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10811418Abstract: A dynamic random access memory (DRAM) cell array using facing bars and a method of fabricating the DRAM cell array are disclosed. A first DRAM cell and a second DRAM cell of each of DRAM cell pairs of a DRAM cell array fabricated using a method of fabricating a DRAM cell array share a facing bar and a bit line plug therebetween. Thus, the overall layout area is greatly reduced by a DRAM cell array fabricated using the method of fabricating the DRAM cell array. Further, in the method of fabricating the DRAM cell array, a storage of each of the DRAM cells of the DRAM cell array is formed as a multi-fin type having a plurality of lateral protrusions, thereby greatly increasing an area of the storage.Type: GrantFiled: April 11, 2018Date of Patent: October 20, 2020Assignee: DOSILICON CO., LTD.Inventors: Jin Ho Kim, Tae Gyoung Kang
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Patent number: 10461091Abstract: A NAND flash memory device having a facing bar and a method of fabricating the same are provided. The method includes forming one transistor or a plurality of stack transistors as cell transistors on two side surfaces of a facing bar to have transmission channels thereat. In this case, the height of the facing bar may be easily increased. Thus, not only a layout area of unit transistors including the cell transistors but also a layout area of cell strings may be minimized, and lengths of the transmission channels of the cell transistors may be sufficiently extended. As a result, according to the NAND flash memory device and the method of fabricating the same, the overall operating characteristics are improved.Type: GrantFiled: December 15, 2017Date of Patent: October 29, 2019Assignee: DOSILICON CO., LTD.Inventors: Jin Ho Kim, Tae Gyoung Kang
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Publication number: 20190237467Abstract: A dynamic random access memory (DRAM) cell array using facing bars and a method of fabricating the DRAM cell array are disclosed. A first DRAM cell and a second DRAM cell of each of DRAM cell pairs of a DRAM cell array fabricated using a method of fabricating a DRAM cell array share a facing bar and a bit line plug therebetween. Thus, the overall layout area is greatly reduced by a DRAM cell array fabricated using the method of fabricating the DRAM cell array. Further, in the method of fabricating the DRAM cell array, a storage of each of the DRAM cells of the DRAM cell array is formed as a multi-fin type having a plurality of lateral protrusions, thereby greatly increasing an area of the storage.Type: ApplicationFiled: April 11, 2018Publication date: August 1, 2019Applicant: DOSILICON CO., LTD.Inventors: Jin Ho Kim, Tae Gyoung Kang
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Publication number: 20190148388Abstract: A NAND flash memory device having a facing bar and a method of fabricating the same are provided. The method includes forming one transistor or a plurality of stack transistors as cell transistors on two side surfaces of a facing bar to have transmission channels thereat. In this case, the height of the facing bar may be easily increased. Thus, not only a layout area of unit transistors including the cell transistors but also a layout area of cell strings may be minimized, and lengths of the transmission channels of the cell transistors may be sufficiently extended. As a result, according to the NAND flash memory device and the method of fabricating the same, the overall operating characteristics are improved.Type: ApplicationFiled: December 15, 2017Publication date: May 16, 2019Applicant: DOSILICON CO., LTD.Inventors: Jin Ho KIM, Tae Gyoung KANG
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Patent number: 10177153Abstract: The fabricating method of a DRAM cell includes forming a facing bar that extends in a direction of the word line; forming a gate of the cell transistor on one side surface of the facing bar; forming a bit line plug that is electrically connected to one side of the transmission channel, which is formed on the one side surface of the facing bar; and forming the storage that is electrically connected to the other side of the transmission channel, which is formed on the horizontal surface of the semiconductor substrate. A pair of DRAM cells shares a facing bar and a bit line plug. In accordance with the present disclosure, a required layout area is significantly reduced.Type: GrantFiled: July 25, 2017Date of Patent: January 8, 2019Assignee: DOSILICON CO., LTD.Inventor: Tae Gyoung Kang
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Publication number: 20180033791Abstract: The fabricating method of a DRAM cell includes forming a facing bar that extends in a direction of the word line; forming a gate of the cell transistor on one side surface of the facing bar; forming a bit line plug that is electrically connected to one side of the transmission channel, which is formed on the one side surface of the facing bar; and forming the storage that is electrically connected to the other side of the transmission channel, which is formed on the horizontal surface of the semiconductor substrate. A pair of DRAM cells shares a facing bar and a bit line plug. In accordance with the present disclosure, a required layout area is significantly reduced.Type: ApplicationFiled: July 25, 2017Publication date: February 1, 2018Applicant: DOSILICON CO., LTD.Inventor: Tae Gyoung KANG
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Patent number: 9087589Abstract: A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of select connection portions corresponding thereto are disposed in one common active region. In the flash memory device, since the number of insulation regions/layout areas for distinguishing active regions is reduced, a layout length in the vertical direction is reduced, ultimately reducing an entire required layout area considerably.Type: GrantFiled: January 14, 2014Date of Patent: July 21, 2015Assignees: FIDELIX CO., LTD., NEMOSTECH CO., LTD.Inventors: Tae Gyoung Kang, Hoon Mo Yoon
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Publication number: 20140233313Abstract: A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of select connection portions corresponding thereto are disposed in one common active region. In the flash memory device, since the number of insulation regions/layout areas for distinguishing active regions is reduced, a layout length in the vertical direction is reduced, ultimately reducing an entire required layout area considerably.Type: ApplicationFiled: January 14, 2014Publication date: August 21, 2014Applicants: Nemostech Co., Ltd., FIDELIX CO., LTD.Inventors: Tae Gyoung KANG, Hoon Mo YOON
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Patent number: 7274580Abstract: A ternary content addressable memory (TCAM) device comprising a plurality of TCAM cells for storing data, each TCAM cell having two memory cells and a comparison circuit for comparing between data stored in the memory cells and data input on a search line pair connected to the comparison circuit, wherein the comparison circuit comprises a first plurality of MOS transistors connected between a match line and a second plurality of MOS transistors, the second plurality of MOS transistors being connected to ground, wherein the first plurality of MOS transistors are gated by signals from the memory cells connected thereto and the second plurality of transistors are gated by signals from a search line pair. The TCAM device includes redundant memory cells which replaces by corresponding column memory cells determined to be defective. Each line of a search line pair is connected to a defective cell is discharged to ground.Type: GrantFiled: November 14, 2005Date of Patent: September 25, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-gyoung Kang, Uk-rae Cho
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Publication number: 20060062038Abstract: A ternary content addressable memory (TCAM) device comprising a plurality of TCAM cells for storing data, each TCAM cell having two memory cells and a comparison circuit for comparing between data stored in the memory cells and data input on a search line pair connected to the comparison circuit, wherein the comparison circuit comprises a first plurality of MOS transistors connected between a match line and a second plurality of MOS transistors, the second plurality of MOS transistors being connected to ground, wherein the first plurality of MOS transistors are gated by signals from the memory cells connected thereto and the second plurality of transistors are gated by signals from a search line pair. The TCAM device includes redundant memory cells which replaces by corresponding column memory cells determined to be defective. Each line of a search line pair is connected to a defective cell is discharged to ground.Type: ApplicationFiled: November 14, 2005Publication date: March 23, 2006Inventors: Tae-gyoung Kang, Uk-rae Cho
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Patent number: 7002822Abstract: A ternary content addressable memory (TCAM) device comprising a plurality of TCAM cells for storing data, each TCAM cell having two memory cells and a comparison circuit for comparing between data stored in the memory cells and data input on a search line pair connected to the comparison circuit, wherein the comparison circuit comprises a first plurality of MOS transistors connected between a match line and a second plurality of MOS transistors, the second plurality of MOS transistors being connected to ground, wherein the first plurality of MOS transistors are gated by signals from the memory cells connected thereto and the second plurality of transistors are gated by signals from a search line pair. The TCAM device includes redundant memory cells which replaces by corresponding column memory cells determined to be defective. Each line of a search line pair is connected to a defective cell is discharged to ground.Type: GrantFiled: August 20, 2003Date of Patent: February 21, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-gyoung Kang, Uk-rae Cho
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Patent number: 6872990Abstract: A semiconductor device layout involving the following: arranging active regions of a plurality of transistors having at least more than one first and second electrodes disposed on a substrate; arranging a plurality of gates of transistors between more than one first and second electrodes of those active regions respectively by positioning at least more than one gates having predetermined width and length at a constant gap on the substrate; and arranging a plurality of dummy gates having predetermined width and length between a plurality of transistors (or between and outside transistors) at the same gap as that of the gates of transistors on the substrate, so that all the gates of transistors are arranged at a constant gap to minimize the variance of process deviations and accordingly reduce the difference of threshold voltage of transistors, thereby increasing reliability of the semiconductor device.Type: GrantFiled: December 9, 1999Date of Patent: March 29, 2005Assignee: Samsung Electronics Co., Ltd.Inventor: Tae-Gyoung Kang
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Publication number: 20050024976Abstract: A ternary content addressable memory (TCAM) device comprising a plurality of TCAM cells for storing data, each TCAM cell having two memory cells and a comparison circuit for comparing between data stored in the memory cells and data input on a search line pair connected to the comparison circuit, wherein the comparison circuit comprises a first plurality of MOS transistors connected between a match line and a second plurality of MOS transistors, the second plurality of MOS transistors being connected to ground, wherein the first plurality of MOS transistors are gated by signals from the memory cells connected thereto and the second plurality of transistors are gated by signals from a search line pair. The TCAM device includes redundant memory cells which replaces by corresponding column memory cells determined to be defective. Each line of a search line pair is connected to a defective cell is discharged to ground.Type: ApplicationFiled: August 20, 2003Publication date: February 3, 2005Inventors: Tae-Gyoung Kang, Uk-Rae Cho
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Patent number: 6393575Abstract: A semiconductor device comprises a plurality of input/output pads, and a plurality of input buffers for receiving external signals synchronized with a clock signal through corresponding ones of the input/output pads, wherein the input buffers are arranged adjacent to each other to minimize skewing of the clock signal to the input buffers.Type: GrantFiled: December 18, 1998Date of Patent: May 21, 2002Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Gyoung Kang, Hee-Choul Park