Abstract: Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure.

Abstract: In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate.

Abstract: In an SOI-type semiconductor device and a method of forming the same a semiconductor device is formed in an SOI-type substrate that is composed of a lower silicon layer, a buried oxide layer, and an SOI layer. The SOI substrate includes a device region isolated by a device isolation layer and the buried oxide layer, in which a source/drain region for forming at least one MOSFET at a body composed of the SOI layer is formed; and a ground region which is isolated from the device region by the device isolation layer and is composed of the body. A bottom portion of the device isolation layer is separated from the buried oxide layer by a connecting portion that electrically connects a body of the device region to a body of the ground region through the SOI layer. A silicon germanium layer is formed in the SOI layer, and at least partially remains at the SOI layer connecting the body of the device region to the body of the ground region in the connecting portion.

Abstract: A method of forming a single crystalline silicon pattern using a structural selective epitaxial growth technique and a selective silicon etching technique, wherein an insulating layer pattern is formed on a semiconductor substrate; polycrystalline silicon is grown on the insulating layer pattern and simultaneously, single crystalline silicon is grown on the semiconductor substrate between the insulating layer patterns. Then, the polycrystalline silicon is removed from the insulating layer pattern. Preferably, the growing of the silicon is performed at a temperature of between about 700 to about 750° C. and a pressure of between about 5 to about 200 Torr. Removing the polycrystalline silicon is performed at a temperature of between about 700 to about 800° C. employing an etch recipe in which polycrystalline silicon has a faster etching rate than single crystalline silicon.

Abstract: The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.

Abstract: A SOI substrate having an etch stopping layer, a SOI integrated circuit fabricated on the SOI substrate, and a method of fabricating both are provided. The SOI substrate includes a supporting substrate, an etch stopping layer staked on the supporting substrate, a buried oxide layer and a semiconductor layer sequentially stacked on the etch stopping layer. The etch stopping layer preferably has an etch selectivity with respect to the buried oxide layer. A device isolation layer is preferably formed to define active regions. The device isolation, buried oxide and etch-stop layers are selectively removed to form first and second holes exposing the supporting substrate without damaging it. Semiconductor epitaxial layers grown on the exposed supporting substrate therefore have single crystalline structures without crystalline defects. Thus, when impurity regions are formed at surfaces of the epitaxial layers, a high performance PN diode having a superior leakage current characteristic may be formed.

Abstract: A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern.

Abstract: In an SOI-type semiconductor device and a method of forming the same a semiconductor device is formed in an SOI-type substrate that is composed of a lower silicon layer, a buried oxide layer, and an SOI layer. The SOI substrate includes a device region isolated by a device isolation layer and the buried oxide layer, in which a source/drain region for forming at least one MOSFET at a body composed of the SOI layer is formed; and a ground region which is isolated from the device region by the device isolation layer and is composed of the body. A bottom portion of the device isolation layer is separated from the buried oxide layer by a connecting portion that electrically connects a body of the device region to a body of the ground region through the SOI layer. A silicon germanium layer is formed in the SOI layer, and at least partially remains at the SOI layer connecting the body of the device region to the body of the ground region in the connecting portion.

Abstract: In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate.