Patents by Inventor Tae Hee YOO
Tae Hee YOO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130164Abstract: A display device includes a substrate and a plurality of unit pixels disposed on the substrate. Each unit pixel includes a plurality of sub-pixels, a plurality of light sensing pixels, and a plurality of partition wall members. Each of the sub-pixels includes a light emitting element that emits light and a light emitting area from which the light is emitted. Each of the light sensing pixels includes a light receiving element that outputs a sensing signal corresponding to the light and a light receiving area that receives the light. In a plan view, each of the partition wall members surrounds the corresponding light receiving area and overlaps at least some of the sub-pixels.Type: ApplicationFiled: July 17, 2023Publication date: April 18, 2024Inventors: Byung Han YOO, Jung Woo PARK, Tae Kyung AHN, Gun Hee KIM, Dae Young LEE
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Patent number: 11961679Abstract: A multilayer capacitor includes a body including a plurality of dielectric layers and a plurality of internal electrodes stacked in a first direction, and external electrodes, wherein the body includes an active portion, a side margin portion covering at least one of a first surface and a second surface of the active portion opposing each other in a second direction, and a cover portion covering the active portion in the first direction, respective dielectric layers among the plurality of dielectric layers include a barium titanate-based composition, the dielectric layer of the side margin portion includes Sn, and a content of Sn in the dielectric layer of the side margin portion is different from that of Sn in the dielectric layer of the active portion, and the dielectric layer of the side margin portion includes at least some grains having a core-shell structure.Type: GrantFiled: November 2, 2021Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin Woo Kim, Eun Jung Lee, Jong Suk Jeong, Chun Hee Seo, Jong Hoon Yoo, Tae Hyung Kim, Ho Sam Choi, Sim Chung Kang
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Patent number: 11938827Abstract: The present disclosure relates to a system for controlling a motor of a vehicle for increasing control accuracy of the motor for driving the vehicle, and an object of the present disclosure is to provide a system for controlling a motor of a vehicle, which may accurately perform a motor control even when a battery voltage (i.e., motor voltage) applied to the motor upon the driving control of the motor is changed.Type: GrantFiled: July 13, 2022Date of Patent: March 26, 2024Assignees: Hyundai Motor Company, Kia CorporationInventors: Ho Sun Jang, Han Hee Park, Seong Min Kim, Ho Rim Choi, Seon Mi Lee, Tae Il Yoo, Seung Hyeon Bin
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Publication number: 20230337367Abstract: A method of manufacturing a printed circuit board includes: forming first and second resist films, respectively having first and second openings exposing a first metal layer disposed on one surface of an insulating layer; forming a second metal layer on the first metal layer, exposed through the first and second openings, to fill at least a portion of each of the first and second openings; and removing the first and second resist films. The first and second openings have different widths in a cross-section.Type: ApplicationFiled: July 20, 2022Publication date: October 19, 2023Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Mi Jeong JEON, Tae Hee YOO, Hyun Seok YANG, In Jae CHUNG
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Patent number: 11195845Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface. The method also includes forming a barrier layer on the stepped structure, forming a mask layer on the barrier layer and exposing at least a portion of the barrier layer by etching at least a portion of the mask layer with a first etching solution The method further includes etching the exposed barrier layer with a second etching solution and etching the mask layer with a third etching solution.Type: GrantFiled: October 16, 2020Date of Patent: December 7, 2021Assignee: ASM IP HOLDING B.V.Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo
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Patent number: 10950432Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.Type: GrantFiled: June 9, 2020Date of Patent: March 16, 2021Assignee: ASM IP Holding B.V.Inventors: Young Hoon Kim, Yong Gyu Han, Dae Youn Kim, Tae Hee Yoo, Wan Gyu Lim, Jin Geun Yu
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Publication number: 20210035988Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface.Type: ApplicationFiled: October 16, 2020Publication date: February 4, 2021Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo
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Patent number: 10847529Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in the process of selectively depositing a landing pad in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface. The method also includes forming a barrier layer on the stepped structure, forming a mask layer on the barrier layer and exposing at least a portion of the barrier layer by etching at least a portion of the mask layer with a first etching solution The method further includes etching the exposed barrier layer with a second etching solution and etching the mask layer with a third etching solution.Type: GrantFiled: April 12, 2018Date of Patent: November 24, 2020Assignee: ASM IP Holding B.V.Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo
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Publication number: 20200303180Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.Type: ApplicationFiled: June 9, 2020Publication date: September 24, 2020Inventors: Young Hoon Kim, Yong Gyu Han, Dae Youn Kim, Tae Hee Yoo, Wan Gyu Lim, Jin Geun Yu
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Patent number: 10734244Abstract: Provided is a substrate processing method capable of preventing over-etching of a part of a stair-case structure due to an etching solution, when a barrier layer is selectively formed on a VNAND device having the stair-case structure. The substrate processing method includes: alternately stacking a first insulating layer and a second insulating layer; forming a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface to the lower surface by etching the first insulating layer and the second insulating layer that are stacked; densifying the stepped structure; forming a barrier layer on the densified second insulating layer; and performing isotropic etching on at least a part of a sacrificial word line structure including the second insulating layer and the barrier layer. During etching the barrier layer at the isotropic etching step, the second insulating layer is not etched or etched a little to an ignorable degree.Type: GrantFiled: July 19, 2018Date of Patent: August 4, 2020Assignee: ASM IP Holding B.V.Inventors: Young Hoon Kim, Jong Wan Choi, Jeong Jun Woo, Tae Hee Yoo
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Patent number: 10714335Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.Type: GrantFiled: April 10, 2018Date of Patent: July 14, 2020Assignee: ASM IP Holding B.V.Inventors: Young Hoon Kim, Yong Gyu Han, Dae Youn Kim, Tae Hee Yoo, Wan Gyu Lim, Jin Geun Yu
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Patent number: 10644025Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.Type: GrantFiled: September 28, 2018Date of Patent: May 5, 2020Assignee: ASM IP Holding B.V.Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo
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Patent number: 10622375Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.Type: GrantFiled: November 13, 2018Date of Patent: April 14, 2020Assignee: ASM IP Holding B.V.Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo
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Patent number: 10504901Abstract: A substrate processing method includes stacking a plurality of stack structures each including an insulating layer and a sacrificial layer, on one another. The method also includes generating a stair structure by etching the stack structures and generating a separation layer on a side surface of the stair structure. The method further includes removing the sacrificial layer and generating conductive word line structures in spaces from which the sacrificial layer is removed. The separation layer is provided between the conductive word line structures.Type: GrantFiled: April 12, 2018Date of Patent: December 10, 2019Assignee: ASM IP HOLDING B.V.Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo
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Publication number: 20190148398Abstract: Provided is a substrate processing method capable of preventing over-etching of a part of a stair-case structure due to an etching solution, when a barrier layer is selectively formed on a VNAND device having the stair-case structure. The substrate processing method includes: alternately stacking a first insulating layer and a second insulating layer; forming a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface to the lower surface by etching the first insulating layer and the second insulating layer that are stacked; densifying the stepped structure; forming a barrier layer on the densified second insulating layer; and performing isotropic etching on at least a part of a sacrificial word line structure including the second insulating layer and the barrier layer. During etching the barrier layer at the isotropic etching step, the second insulating layer is not etched or etched a little to an ignorable degree.Type: ApplicationFiled: July 19, 2018Publication date: May 16, 2019Inventors: Young Hoon Kim, Jong Wan Choi, Jeong Jun Woo, Tae Hee Yoo
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Publication number: 20190115206Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.Type: ApplicationFiled: April 10, 2018Publication date: April 18, 2019Inventors: Young Hoon Kim, Yong Gyu Han, Dae Youn Kim, Tae Hee Yoo, Wan Gyu Lim, Jin Geun Yu
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Publication number: 20190081072Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.Type: ApplicationFiled: November 13, 2018Publication date: March 14, 2019Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo
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Publication number: 20190035810Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.Type: ApplicationFiled: September 28, 2018Publication date: January 31, 2019Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo
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Patent number: 10134757Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.Type: GrantFiled: June 30, 2017Date of Patent: November 20, 2018Assignee: ASM IP Holding B.V.Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo
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Publication number: 20180315758Abstract: A substrate processing method includes stacking a plurality of stack structures each including an insulating layer and a sacrificial layer, on one another. The method also includes generating a stair structure by etching the stack structures and generating a separation layer on a side surface of the stair structure. The method further includes removing the sacrificial layer and generating conductive word line structures in spaces from which the sacrificial layer is removed. The separation layer is provided between the conductive word line structures.Type: ApplicationFiled: April 12, 2018Publication date: November 1, 2018Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo