Patents by Inventor Tae Hee YOO

Tae Hee YOO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240215158
    Abstract: A printed circuit board includes a first insulating layer, a first metal layer disposed on the first insulating layer and including a first oxidation region on a side surface thereof, and a second metal layer disposed on the first metal layer. A method of manufacturing a printed circuit board includes forming a first metal layer on a first insulating layer, forming a second metal layer on a portion of the first metal layer, oxidizing another portion of the first metal layer to form a first oxidation region, and removing at least a portion of the first oxidation region.
    Type: Application
    Filed: June 14, 2023
    Publication date: June 27, 2024
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Mi Jeong JEON, Hyun Seok YANG, Tae Hee YOO, Chan Jin PARK
  • Patent number: 12022621
    Abstract: A method of manufacturing a printed circuit board includes: forming first and second resist films, respectively having first and second openings exposing a first metal layer disposed on one surface of an insulating layer; forming a second metal layer on the first metal layer, exposed through the first and second openings, to fill at least a portion of each of the first and second openings; and removing the first and second resist films. The first and second openings have different widths in a cross-section.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: June 25, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Mi Jeong Jeon, Tae Hee Yoo, Hyun Seok Yang, In Jae Chung
  • Publication number: 20240164013
    Abstract: A printed circuit board including a first insulating layer; a plurality of first circuit patterns respectively disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer and covering a portion of a side surface of each of the plurality of first circuit patterns; and an insulator disposed between at least one pair of adjacent first circuit patterns, among the plurality of first circuit patterns, and integrated with the first insulating layer, and a method for manufacturing a printed circuit board, are provided.
    Type: Application
    Filed: July 12, 2023
    Publication date: May 16, 2024
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Heun LEE, Jong Eun PARK, Chan Jin PARK, Hyun Seok YANG, Tae Hee YOO
  • Publication number: 20230337367
    Abstract: A method of manufacturing a printed circuit board includes: forming first and second resist films, respectively having first and second openings exposing a first metal layer disposed on one surface of an insulating layer; forming a second metal layer on the first metal layer, exposed through the first and second openings, to fill at least a portion of each of the first and second openings; and removing the first and second resist films. The first and second openings have different widths in a cross-section.
    Type: Application
    Filed: July 20, 2022
    Publication date: October 19, 2023
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Mi Jeong JEON, Tae Hee YOO, Hyun Seok YANG, In Jae CHUNG
  • Patent number: 11195845
    Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface. The method also includes forming a barrier layer on the stepped structure, forming a mask layer on the barrier layer and exposing at least a portion of the barrier layer by etching at least a portion of the mask layer with a first etching solution The method further includes etching the exposed barrier layer with a second etching solution and etching the mask layer with a third etching solution.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: December 7, 2021
    Assignee: ASM IP HOLDING B.V.
    Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo
  • Patent number: 10950432
    Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: March 16, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Young Hoon Kim, Yong Gyu Han, Dae Youn Kim, Tae Hee Yoo, Wan Gyu Lim, Jin Geun Yu
  • Publication number: 20210035988
    Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface.
    Type: Application
    Filed: October 16, 2020
    Publication date: February 4, 2021
    Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo
  • Patent number: 10847529
    Abstract: Provided is a substrate processing method that may prevent the non-uniformity of the thickness of landing pads deposited on each step in the process of selectively depositing a landing pad in a vertical NAND device having a stepped structure. The substrate processing method includes stacking, a plurality of times, a stack structure including an insulating layer and a sacrificial layer and etching the stack structure to form a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface. The method also includes forming a barrier layer on the stepped structure, forming a mask layer on the barrier layer and exposing at least a portion of the barrier layer by etching at least a portion of the mask layer with a first etching solution The method further includes etching the exposed barrier layer with a second etching solution and etching the mask layer with a third etching solution.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 24, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo
  • Publication number: 20200303180
    Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Inventors: Young Hoon Kim, Yong Gyu Han, Dae Youn Kim, Tae Hee Yoo, Wan Gyu Lim, Jin Geun Yu
  • Patent number: 10734244
    Abstract: Provided is a substrate processing method capable of preventing over-etching of a part of a stair-case structure due to an etching solution, when a barrier layer is selectively formed on a VNAND device having the stair-case structure. The substrate processing method includes: alternately stacking a first insulating layer and a second insulating layer; forming a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface to the lower surface by etching the first insulating layer and the second insulating layer that are stacked; densifying the stepped structure; forming a barrier layer on the densified second insulating layer; and performing isotropic etching on at least a part of a sacrificial word line structure including the second insulating layer and the barrier layer. During etching the barrier layer at the isotropic etching step, the second insulating layer is not etched or etched a little to an ignorable degree.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: August 4, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Young Hoon Kim, Jong Wan Choi, Jeong Jun Woo, Tae Hee Yoo
  • Patent number: 10714335
    Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: July 14, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Young Hoon Kim, Yong Gyu Han, Dae Youn Kim, Tae Hee Yoo, Wan Gyu Lim, Jin Geun Yu
  • Patent number: 10644025
    Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 5, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo
  • Patent number: 10622375
    Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 14, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo
  • Patent number: 10504901
    Abstract: A substrate processing method includes stacking a plurality of stack structures each including an insulating layer and a sacrificial layer, on one another. The method also includes generating a stair structure by etching the stack structures and generating a separation layer on a side surface of the stair structure. The method further includes removing the sacrificial layer and generating conductive word line structures in spaces from which the sacrificial layer is removed. The separation layer is provided between the conductive word line structures.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: December 10, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo
  • Publication number: 20190148398
    Abstract: Provided is a substrate processing method capable of preventing over-etching of a part of a stair-case structure due to an etching solution, when a barrier layer is selectively formed on a VNAND device having the stair-case structure. The substrate processing method includes: alternately stacking a first insulating layer and a second insulating layer; forming a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface to the lower surface by etching the first insulating layer and the second insulating layer that are stacked; densifying the stepped structure; forming a barrier layer on the densified second insulating layer; and performing isotropic etching on at least a part of a sacrificial word line structure including the second insulating layer and the barrier layer. During etching the barrier layer at the isotropic etching step, the second insulating layer is not etched or etched a little to an ignorable degree.
    Type: Application
    Filed: July 19, 2018
    Publication date: May 16, 2019
    Inventors: Young Hoon Kim, Jong Wan Choi, Jeong Jun Woo, Tae Hee Yoo
  • Publication number: 20190115206
    Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.
    Type: Application
    Filed: April 10, 2018
    Publication date: April 18, 2019
    Inventors: Young Hoon Kim, Yong Gyu Han, Dae Youn Kim, Tae Hee Yoo, Wan Gyu Lim, Jin Geun Yu
  • Publication number: 20190081072
    Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.
    Type: Application
    Filed: November 13, 2018
    Publication date: March 14, 2019
    Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo
  • Publication number: 20190035810
    Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.
    Type: Application
    Filed: September 28, 2018
    Publication date: January 31, 2019
    Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo
  • Patent number: 10134757
    Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: November 20, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo
  • Publication number: 20180315758
    Abstract: A substrate processing method includes stacking a plurality of stack structures each including an insulating layer and a sacrificial layer, on one another. The method also includes generating a stair structure by etching the stack structures and generating a separation layer on a side surface of the stair structure. The method further includes removing the sacrificial layer and generating conductive word line structures in spaces from which the sacrificial layer is removed. The separation layer is provided between the conductive word line structures.
    Type: Application
    Filed: April 12, 2018
    Publication date: November 1, 2018
    Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo