Patents by Inventor Taehee YOU

Taehee YOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10615801
    Abstract: A technology mapping method for a FPGA includes converting a gate level netlist into an AND-Inverter Graph (AIG) netlist, selecting a node among nodes included in the AIG netlist, generating a cut set including one or more cuts corresponding to the selected node, selecting a best cut by sorting the cuts included in the cut set according to predetermined criteria and outputting a LUT netlist including the best cut, wherein the predetermined criteria include a maximum difference of levels of sub-cuts connected in each cut as a first criterion.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: April 7, 2020
    Assignees: SK hynix Inc., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Kangwook Jo, Jeongbin Kim, Minyoung Im, Taehee You, Eui-Young Chung, Hongil Yoon
  • Patent number: 10554395
    Abstract: A semiconductor device may comprise a plurality of chips coupled in a ring structure, and the plurality of chips includes a first chip. Each of the plurality of chips may include a key port receiving or outputting a key to circulate the key through the ring structure. The first chip is configured to be in a standby state until an amount of available token becomes equal to or greater than an amount of required token to perform a specific operation in the first chip, when the first chip has the key.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: February 4, 2020
    Assignees: SK Hynix Inc., Industry-Academic Cooperation Foundation Yonsei University
    Inventors: Taehee You, Sangwoo Han, Youngmin Park, Eui-Young Chung, Jaewoo Park, Byungryul Kim, Younghwan Hong
  • Publication number: 20190356316
    Abstract: A technology mapping method for a FPGA includes converting a gate level netlist into an AND-Inverter Graph (AIG) netlist, selecting a node among nodes included in the AIG netlist, generating a cut set including one or more cuts corresponding to the selected node, selecting a best cut by sorting the cuts included in the cut set according to predetermined criteria and outputting a LUT netlist including the best cut, wherein the predetermined criteria include a maximum difference of levels of sub-cuts connected in each cut as a first criterion.
    Type: Application
    Filed: August 1, 2019
    Publication date: November 21, 2019
    Inventors: Kangwook JO, Jeongbin KIM, Minyoung IM, Taehee YOU, Eui-Young CHUNG, Hongil YOON
  • Patent number: 10419001
    Abstract: A look up table (LUT) includes a decoder configured to decode input signals and to output decoded signals, a storage unit including a plurality of magnetic elements an being configured to select one or more of the plurality of magnetic elements in response to the decoded signals and a signal input/output (TO) unit configured to output an output signal corresponding to the selected one or more magnetic elements and to program the selected one or more magnetic elements by receiving a write signal.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: September 17, 2019
    Assignees: SK Hynix Inc., Industry-Academic Cooperation Foundation Yonsei University
    Inventors: Kangwook Jo, Jeongbin Kim, Minyoung Im, Taehee You, Eui-Young Chung, Hongil Yoon
  • Patent number: 10379585
    Abstract: A semiconductor device may comprise a plurality of chips coupled in a bidirectional ring structure. The plurality of chips includes a first chip, and the first chip determines whether a token is required to perform a specific operation in the first chip. The first chip further determines whether an amount of an available token in the first chip is equal to or greater than an amount of the required token to perform the specific operation. When the amount of the available token is equal to or greater than the amount of the required token, the first chip performs the specific operation and then the first chip outputs one or both of a first portion of the available token in a first direction and a second portion of the available token in a second direction. The first direction is opposite to the second direction in the bidirectional ring structure.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: August 13, 2019
    Assignee: SK HYNIX INC.
    Inventors: Taehee You, Sangwoo Han, Youngmin Park, Eui-Young Chung, Jaewoo Park, Byungryul Kim, Younghwan Hong
  • Publication number: 20180287614
    Abstract: A look up table (LUT) includes a decoder configured to decode input signals and to output decoded signals, a storage unit including a plurality of magnetic elements an being configured to select one or more of the plurality of magnetic elements in response to the decoded signals and a signal input/output (TO) unit configured to output an output signal corresponding to the selected one or more magnetic elements and to program the selected one or more magnetic elements by receiving a write signal.
    Type: Application
    Filed: November 2, 2017
    Publication date: October 4, 2018
    Inventors: Kangwook JO, Jeongbin KIM, Minyoung IM, Taehee YOU, Eui-Young CHUNG, Hongil YOON
  • Publication number: 20170277243
    Abstract: A semiconductor device may comprise a plurality of chips coupled in a bidirectional ring structure. The plurality of chips includes a first chip, and the first chip determines whether a token is required to perform a specific operation in the first chip. The first chip further determines whether an amount of an available token in the first chip is equal to or greater than an amount of the required token to perform the specific operation. When the amount of the available token is equal to or greater than the amount of the required token, the first chip performs the specific operation and then the first chip outputs one or both of a first portion of the available token in a first direction and a second portion of the available token in a second direction. The first direction is opposite to the second direction in the bidirectional ring structure.
    Type: Application
    Filed: March 8, 2017
    Publication date: September 28, 2017
    Inventors: Taehee YOU, Sangwoo HAN, Youngmin PARK, Eui-Young CHUNG, Jaewoo PARK, Byungryul KIM, Younghwan HONG
  • Publication number: 20170277244
    Abstract: A semiconductor device may comprise a plurality of chips coupled in a ring structure, and the plurality of chips includes a first chip. Each of the plurality of chips may include a key port receiving or outputting a key to circulate the key through the ring structure. The first chip is configured to be in a standby state until an amount of available token becomes equal to or greater than an amount of required token to perform a specific operation in the first chip, when the first chip has the key.
    Type: Application
    Filed: March 8, 2017
    Publication date: September 28, 2017
    Inventors: Taehee YOU, Sangwoo HAN, Youngmin PARK, Eui-Young CHUNG, Jaewoo PARK, Byungryul KIM, Younghwan HONG