Abstract: An embodiment discloses a display apparatus. The display apparatus includes a plurality of first electrodes and a contact electrode disposed on a substrate. The display apparatus includes a plurality of light-emitting elements disposed on the plurality of first electrodes. The display apparatus includes a first optical layer disposed between the plurality of light-emitting elements. The display apparatus includes a second electrode disposed on the plurality of light-emitting elements. The second electrode includes a first area disposed on the plurality of light-emitting elements and a second area extending outward from the first optical layer and electrically connected to the contact electrode. A plurality of signal wires connected to the plurality of first electrodes are provided, the second area of the second electrode comprises protruding portions extending to at least one of areas between the plurality of signal wires, and one of the protruding portions is connected to the contact electrode.

Abstract: A display device includes a plurality of first electrodes and a contact electrode on a substrate; a plurality of light-emitting elements on the plurality of first electrodes; a first optical layer between the plurality of light-emitting elements; and a second electrode on the plurality of light-emitting elements, the second electrode including a first region that is on the plurality of light-emitting elements and a second region that extends past an end the first optical layer and is in contact with the contact electrode.

Abstract: A mother substrate for a display panel and a display panel using the same are disclosed. The mother substrate comprises a plurality of display area including a plurality of light-emitting areas configured to receive light-emitting elements, a plurality of wirings, and a plurality of pads connected to the plurality of wirings; a conductive ring in a non-display area that surrounds the display area such that each of the display areas is surrounded by the conductive ring and electrically connected to the pads; a photoresist pattern covering the plurality of display areas and the non-display area; and a first metal layer covering the photoresist pattern. The conductive ring includes an electrostatic blocking area.

Abstract: An object of the present invention is to provide a material for organic EL elements, the material being excellent in hole injecting/transporting performance, electron-blocking capability, stability in the form of a thin film, and durability. Another object of the present invention is to provide an organic EL element having high efficiency, a low driving voltage, and a long lifespan, by combining the aforementioned material with various materials for organic EL elements, the materials being excellent in hole/electron injecting/transporting performance, electron-blocking capability, stability in the form of a thin film, and durability, such that the properties of the individual materials can be effectively exhibited.

Abstract: An anti-inflammatory composition according to an embodiment includes natural organic calcium carbonate, and thus provides the advantages that the composition can be consumed as food, is completely harmless to the human body, and can significantly treat or alleviate inflammations in human and animal cells. Also, the anti-inflammatory composition can promote metabolisms of cells and eliminate active oxygen in the body while treating inflammations. Since the anti-inflammatory composition can be preserved easily because it is not sensitive to the surrounding environment and is resistant to degradation even when exposed to the atmosphere, the anti-inflammatory composition can be added to various beverages or food materials. Furthermore, when the anti-inflammatory composition is added to food materials, a high degree of freshness of food can be preserved for a long time by preventing the oxidation thereof, and also has the effect of restoring oxidized skin and damaged skin through reduction.

Abstract: A nonvolatile memory cell and a method for fabricating the same can secure stable operational reliability as well as reducing a cell size. The nonvolatile memory cell includes a drain region formed in a substrate, a source region formed in the substrate to be separated from the drain region, a floating gate formed over the substrate between the drain region and the source region, a halo region formed in the substrate in a direction that the drain region is formed, a dielectric layer formed on sidewalls of the floating gate, and a control gate formed over the dielectric layer to overlap with at least one sidewall of the floating gate.

Abstract: A nonvolatile memory cell and a method for fabricating the same can secure stable operational reliability as well as reducing a cell size. The nonvolatile memory cell includes a drain region formed in a substrate, a source region formed in the substrate to be separated from the drain region, a floating gate formed over the substrate between the drain region and the source region, a halo region formed in the substrate in a direction that the drain region is formed, a dielectric layer formed on sidewalls of the floating gate, and a control gate formed over the dielectric layer to overlap with at least one sidewall of the floating gate.

Abstract: A method of fabricating a nonvolatile memory device including forming a plurality of device isolation layers in a semiconductor substrate to define a plurality of active regions, sequentially depositing an insulating layer and a first conductive layer on the semiconductor substrate, and forming a hard mask pattern on the first conductive layer. The method also includes forming a plurality of floating gates on the insulating layer by etching the first conductive layer using the hard mask pattern as a mask, forming a tunnel insulating layer on the semiconductor substrate including floating gates and the insulating layer, and depositing a second conductive layer on the tunnel insulating layer. The method further includes forming a plurality of control gate electrodes across the active regions by etching the second conductive layer, forming source and drain regions in the semiconductor substrate by performing an ion implantation, and forming contacts in the drain regions.

Abstract: A method of fabricating a nonvolatile memory device including forming a plurality of device isolation layers in a semiconductor substrate to define a plurality of active regions, sequentially depositing an insulating layer and a first conductive layer on the semiconductor substrate, and forming a hard mask pattern on the first conductive layer. The method also includes forming a plurality of floating gates on the insulating layer by etching the first conductive layer using the hard mask pattern as a mask, forming a tunnel insulating layer on the semiconductor substrate including floating gates and the insulating layer, and depositing a second conductive layer on the tunnel insulating layer. The method further includes forming a plurality of control gate electrodes across the active regions by etching the second conductive layer, forming source and drain regions in the semiconductor substrate by performing an ion implantation, and forming contacts in the drain regions.

Abstract: Nonvolatile semiconductor memory devices and methods of manufacturing the same are disclosed. A disclosed nonvolatile semiconductor memory cell includes a semiconductor substrate; first and second semiconductor cells positioned on the semiconductor substrate at a distance from each other; a first source and a second source adjacent the first and second semiconductor cells; a first drain contact between the first and second semiconductor cells; first and second cap dielectrics formed on the first and second semiconductor cells, respectively; first and second sidewall spacers formed on sidewalls of the first and second semiconductor cells, respectively; an inter metal dielectric layer covering the first and second cap dielectrics and the first and second sidewall spacers, a drain contact hole exposing the drain; and a second drain contact connected to the first drain contact through the drain contact hole.

Abstract: A flash memory device fabrication method is disclosed. A disclosed method comprises: forming an oxide layer on a substrate; depositing a first polysilicon on the entire surface of the oxide layer and patterning the first polysilicon; depositing an insulating layer on the entire surface of the first polysilicon and patterning the insulating layer to expose the first polysilicon; depositing a second polysilicon on the entire surface of the resulting structure and patterning the second polysilicon; removing the insulating layer; depositing a dielectric layer on the entire surface of the resulting structure; and depositing a third polysilicon on the entire surface of the dielectric layer.

Abstract: A cell transistor of a flash memory device includes a semiconductor substrate, a source region, a drain region, a floating gate, an inter-gate insulating layer, and a control gate, wherein the floating gate has a tip protruding into an end portion of the source region. With the application of erasing voltages to the source region and the control gate, an intense electric field is induced on the tip of the floating gate. Accordingly, an erasing efficiency of the cell transistor can be enhanced.

Abstract: A cell transistor of a flash memory device includes a semiconductor substrate, a source region, a drain region, a floating gate, an inter-gate insulating layer, and a control gate, wherein the floating gate has a tip protruding into an end portion of the source region. With the application of erasing voltages to the source region and the control gate, an intense electric field is induced on the tip of the floating gate. Accordingly, an erasing efficiency of the cell transistor can be enhanced.

Abstract: A split-gate flash memory cell and a manufacturing method thereof is provided. After a tunnel oxide layer is formed over a substrate, a peak floating gate layer of conducting material is formed over a portion of the tunnel oxide layer. An inter-gate insulating layer and a control gate layer are formed over the peak floating gate layer and then the control gate layer, the inter-gate insulating layer, the peak floating gate layer and the tunnel oxide layer are sequentially etched down to generate a control gate, an inter-gate insulating region, a peak floating gate and a tunnel oxide region. Finally, a source and a drain are defined adjoining the tunnel oxide region by using a self-align technique.

Abstract: A cell transistor of a flash memory device includes a semiconductor substrate, a source region, a drain region, a floating gate, an inter-gate insulating layer, and a control gate, wherein the floating gate has a tip protruding into an end portion of the source region. With the application of erasing voltages to the source region and the control gate, an intense electric field is induced on the tip of the floating gate. Accordingly, an erasing efficiency of the cell transistor can be enhanced.

Abstract: A split-gate flash memory cell and a manufacturing method thereof is provided. After a tunnel oxide layer is formed over a substrate, a peak floating gate layer of conducting material is formed over a portion of the tunnel oxide layer. An inter-gate insulating layer and a control gate layer are formed over the peak floating gate layer and then the control gate layer, the inter-gate insulating layer, the peak floating gate layer and the tunnel oxide layer are sequentially etched down to generate a control gate, an inter-gate insulating region, a peak floating gate and a tunnel oxide region. Finally, a source and a drain are defined adjoining the tunnel oxide region by using a self-align technique.

Abstract: Disclosed is a system of processing, converting and distributing a message in the network hierarchy of a fixed subscriber unit (FSU) in a Broad band Code Division Multiple Access Wireless Local Loop (B-CDMA WLL). The network hierarchy includes first to seven layers. The first layer is provided with a SLIC2, ADPCM/PCM module, MAC module, PHL module and LLME. The second layer is provided with a DLC module. The third layer is provided with a network module. The higher layers are provided with a subscriber module and a retaining module. The network module serves to process and format a message communicated between the LLME and the subscriber or retaining module to distribute the formatted message among the subscriber and retaining modules or conversely to transfer it to the LLME.