Abstract: In general terms, embodiments of the present invention relate to an overvoltage protection circuit. In some embodiments, the overvoltage protection circuit includes: (a) an input receiving node configured to receive an input voltage; (b) an input transmitting node; (c) an input switch formed between the input receiving node and the input transmitting node, and configured to selectively electrically connect the input receiving node to the input transmitting node based on a switch control signal, where the input switch is configured to cut off an electrical connection between the input receiving node and the input transmitting node when the switch control signal is in an inactive state (e.g., a logic low state “L”); and (d) a control signal generation block configured to sense a transmission voltage of the input transmitting node and generate the switch control signal in the inactive state when the transmission voltage rises to a reference voltage or higher.

Abstract: A source driver for use in a display device having a shift register unit for sequentially activating output signals. The shift register unit includes a plurality of shift registers connected in series, wherein Nth shift register among the plurality of shift registers selects one of an output of a (N?1)th shift register and an output of a (N?A)th shift register according to a channel selection signal to thereby receive the selected signal, where A is a natural number which is greater than or equal to 2.

Abstract: A source driver for use in a display device having a shift register unit for sequentially activating output signals. The shift register unit includes a plurality of shift registers connected in series, wherein Nth shift register among the plurality of shift registers selects one of an output of a (N?1)th shift register and an output of a (N?A)th shift register according to a channel selection signal to thereby receive the selected signal, where A is a natural number which is greater than or equal to 2.

Abstract: The source driver for use in an active matrix liquid crystal display includes an input block for generating a pixel data sequence having pixel data transmitted through N numbers of channels as a unit pixel data, a multiplexing block for compressing the pixel data sequence to thereby output through a data bus having data lines corresponding to N/L numbers of channels, a shift register for generating a latch enable signal, and a line latch circuit constituted M numbers of latches receiving the pixel data inputted when the corresponding latch enable signal is inputted, wherein L, M, N are natural numbers, N is multiple number of L, and M is lager than N.