Patents by Inventor Tae-hoi Park

Tae-hoi Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240124062
    Abstract: A vehicle body structure includes: a roof side assembly connecting upper ends of pillars of a vehicle body along the forward/backward direction of the vehicle body, the roof side assembly constituting an A-pillar of the vehicle body; and an outer garnish coupled to the outside of the roof side assembly, wherein the roof side assembly includes: a pipe having a closed cross-section shape and elongated in the forward/backward direction of the vehicle body so as to form a closed section; an upper reinforcement member coupled to the upper side of the pipe and elongated in the forward/backward direction of the vehicle body; a lower reinforcement member coupled to the lower side of the pipe and elongated in the forward/backward direction of the vehicle body; and an inner reinforcement member coupled to the vehicle body inner side of the pipe and elongated in the forward/backward direction of the vehicle body.
    Type: Application
    Filed: April 13, 2023
    Publication date: April 18, 2024
    Applicants: Hyundai Motor Company, Kia Corporation, HYUNDAI MOBIS CO., LTD.
    Inventors: Do Hoi KIM, Sun Ho SONG, Jae Young LIM, Sea Cheoul SONG, Kang Chul LEE, Tae Ou PARK, Jae Sup BYUN, Jang Ho KIM
  • Patent number: 10643888
    Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham
  • Patent number: 10573633
    Abstract: A semiconductor device includes a first overlay group and a second overlay group disposed on a semiconductor substrate. The first overlay group includes first lower overlay patterns which extend in a first direction, first upper overlay patterns overlapping the first lower overlay patterns, and first via overlay patterns interposed between the first lower overlay patterns and the first upper overlay patterns. The second overlay group includes second lower overlay patterns which extend in a second direction, second upper overlay patterns overlapping the second lower overlay patterns, and second via overlay patterns interposed between the second lower overlay patterns and the second upper overlay patterns. The second lower overlay patterns include end portions adjacent to and spaced apart from the first overlay group.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: February 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Sun Kim, Hyun Jae Kang, Tae Hoi Park, Jin Seong Lee, Eun Sol Choi, Min Keun Kwak, Byung Kap Kim, Sung Won Choi
  • Publication number: 20180175016
    Abstract: A semiconductor device includes a first overlay group and a second overlay group disposed on a semiconductor substrate. The first overlay group includes first lower overlay patterns which extend in a first direction, first upper overlay patterns overlapping the first lower overlay patterns, and first via overlay patterns interposed between the first lower overlay patterns and the first upper overlay patterns. The second overlay group includes second lower overlay patterns which extend in a second direction, second upper overlay patterns overlapping the second lower overlay patterns, and second via overlay patterns interposed between the second lower overlay patterns and the second upper overlay patterns. The second lower overlay patterns include end portions adjacent to and spaced apart from the first overlay group.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 21, 2018
    Inventors: Tae Sun Kim, Hyun Jae Kang, Tae Hoi Park, Jin Seong Lee, Eun Sol Choi, Min Keun Kwak, Byung Kap Kim, Sung Won Choi
  • Publication number: 20170278745
    Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.
    Type: Application
    Filed: June 13, 2017
    Publication date: September 28, 2017
    Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham
  • Patent number: 9711395
    Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: July 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham
  • Publication number: 20160035617
    Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.
    Type: Application
    Filed: July 28, 2015
    Publication date: February 4, 2016
    Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham
  • Patent number: 8623739
    Abstract: A method of manufacturing a semiconductor device includes forming a resist pattern on a first region on a substrate, bringing a descum solution including an acid source into contact with the resist pattern and with a second region of the substrate, decomposing resist residues remaining on the second region of the substrate by using acid obtained from the acid source in the descum solution and removing the decomposed resist residues and the descum solution from the substrate.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: January 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-rae Lee, Yool Kang, Kyung-hwan Yoon, Hyoung-hee Kim, So-ra Han, Tae-hoi Park
  • Publication number: 20120028434
    Abstract: A method of manufacturing a semiconductor device includes forming a resist pattern on a first region on a substrate, bringing a descum solution including an acid source into contact with the resist pattern and with a second region of the substrate, decomposing resist residues remaining on the second region of the substrate by using acid obtained from the acid source in the descum solution and removing the decomposed resist residues and the descum solution from the substrate.
    Type: Application
    Filed: July 19, 2011
    Publication date: February 2, 2012
    Inventors: Hyung-rae LEE, Yool Kang, Kyung-hwan Yoon, Hyoung-hee Kim, So-ra Han, Tae-hoi Park