Patents by Inventor Tae-Hong Ha
Tae-Hong Ha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948836Abstract: Apparatuses and methods to provide electronic devices having metal films are provided. Some embodiments of the disclosure utilize a metallic tungsten layer as a liner that is filled with a metal film comprising cobalt. The metallic tungsten layer has good adhesion to the cobalt leading to enhanced cobalt gap-fill performance.Type: GrantFiled: October 11, 2021Date of Patent: April 2, 2024Assignee: Applied Materials, Inc.Inventors: Yu Lei, Sang-Hyeob Lee, Chris Pabelico, Yi Xu, Tae Hong Ha, Xianmin Tang, Jin Hee Park
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Patent number: 11939666Abstract: Methods and apparatus for processing a substrate include cleaning and self-assembly monolayer (SAM) formation for subsequent reverse selective atomic layer deposition. An apparatus may include a process chamber with a processing volume and a substrate support including a pedestal, a remote plasma source fluidly coupled to the process chamber and configured to produce radicals or ionized gas mixture with radicals that flow into the processing volume to remove residue or oxides from a surface of the substrate, a first gas delivery system with a first ampoule configured to provide at least one first chemical into the processing volume to produce a SAM on the surface of the substrate, a heating system located in the pedestal and configured to heat a substrate by flowing gas on a backside of the substrate, and a vacuum system fluidly coupled to the process chamber and configured to control heating of the substrate.Type: GrantFiled: June 1, 2020Date of Patent: March 26, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Xiangjin Xie, Carmen Leal Cervantes, Feng Chen, Lu Chen, Wenjing Xu, Aravind Kamath, Cheng-Hsiung Matthew Tsai, Tae Hong Ha, Alexander Jansen, Xianmin Tang
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Publication number: 20240090121Abstract: A printed circuit board includes a first substrate portion including a plurality of first insulating layers, a plurality of first wiring layers respectively disposed on the plurality of first insulating layers, and a plurality of first adhesive layers respectively disposed between the plurality of first insulating layers to respectively cover the plurality of first wiring layers; and a second substrate portion disposed on the first substrate portion, and including a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on the plurality of second insulating layers, and a plurality of second adhesive layers respectively disposed between the plurality of second insulating layers to respectively cover the plurality of second wiring layers.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Jung BYUN, Jung Soo KIM, Sang Hyun SIM, Chang Min HA, Tae Hong MIN, Jin Won LEE
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Publication number: 20240038859Abstract: A contact stack of a semiconductor device comprises: a source/drain region; a metal silicide layer above the source/drain region; a metal cap layer directly on the metal silicide layer; and a conductor on the metal cap layer. A method comprises: depositing a metal silicide layer in a feature of a substrate; in the absence of an air break after the depositing of the metal silicide layer, preparing a metal cap layer directly on the metal silicide layer; and depositing a conductor on the metal cap layer.Type: ApplicationFiled: October 12, 2023Publication date: February 1, 2024Applicant: Applied Materials, Inc.Inventors: Bencherki Mebarki, Joung Joo Lee, Wenting Hou, Takashi Kuratomi, Avgerinos V. Gelatos, Jianxin Lei, Liqi Wu, Raymond Hoiman Hung, Tae Hong Ha, Xianmin Tang
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Patent number: 11784127Abstract: Electronic devices and methods of forming electronic devices using a ruthenium or doped ruthenium liner and cap layer are described. A liner with a ruthenium layer and a cobalt layer is formed on a barrier layer. A conductive fill forms a second conductive line in contact with the first conductive line.Type: GrantFiled: July 6, 2022Date of Patent: October 10, 2023Assignee: Applied Materials, Inc.Inventors: Wenjing Xu, Feng Chen, Tae Hong Ha, Xianmin Tang, Lu Chen, Zhiyuan Wu
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Patent number: 11764157Abstract: Electronic devices and methods of forming electronic devices using a ruthenium or doped ruthenium liner and cap layer are described. A liner with a ruthenium layer and a cobalt layer is formed on a barrier layer. A conductive fill forms a second conductive line in contact with the first conductive line.Type: GrantFiled: July 22, 2021Date of Patent: September 19, 2023Assignee: Applied Materials, Inc.Inventors: Wenjing Xu, Feng Chen, Tae Hong Ha, Xianmin Tang, Lu Chen, Zhiyuan Wu
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Patent number: 11672132Abstract: A variable resistance memory device includes lower conductive lines extending in a first direction on a substrate and spaced apart from each other in a second direction crossing the first direction, peripheral transistors on the substrate and arranged under the lower conductive lines in a third direction crossing the first direction and the second direction, and lower contacts electrically connecting the lower conductive lines to the peripheral transistors and extending in the third direction. Each of the lower conductive lines includes a first lower extending portion extending in the first direction, a second lower extending portion offset in the second direction from the first lower extending portion and extending in the first direction, and a lower connecting portion connecting the first lower extending portion to the second lower extending portion. Each of the lower contacts is in the lower connecting portion of a respective one of the lower conductive lines.Type: GrantFiled: June 28, 2021Date of Patent: June 6, 2023Inventors: Tae Hong Ha, Jae Rok Kahng
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Patent number: 11587873Abstract: Described are microelectronic devices comprising a dielectric layer formed on a substrate, a feature comprising a gap defined in the dielectric layer, a barrier layer on the dielectric layer, a two metal liner film on the barrier layer and a gap fill metal on the two metal liner. Embodiments provide a method of forming a microelectronic device comprising the two metal liner film on the barrier layer.Type: GrantFiled: June 23, 2020Date of Patent: February 21, 2023Assignee: Applied Materials, Inc.Inventors: Gang Shen, Feng Chen, Yizhak Sabba, Tae Hong Ha, Xianmin Tang, Zhiyuan Wu, Wenjing Xu
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Patent number: 11562909Abstract: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.Type: GrantFiled: May 22, 2020Date of Patent: January 24, 2023Assignee: Applied Materials, Inc.Inventors: Yu Lei, Xuesong Lu, Tae Hong Ha, Xianmin Tang, Andrew Nguyen, Tza-Jing Gung, Philip A. Kraus, Chung Nang Liu, Hui Sun, Yufei Hu
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Patent number: 11527437Abstract: Methods and apparatus for filling features on a substrate are provided herein. In some embodiments, a method of filling features on a substrate includes: depositing a first metallic material on the substrate and within a feature disposed in the substrate in a first process chamber via a chemical vapor deposition (CVD) process at a first temperature; depositing a second metallic material on the first metallic material in a second process chamber at a second temperature and at a first bias power to form a seed layer of the second metallic material; etching the seed layer in the second process chamber at a second bias power greater than the first bias power to form an intermix layer within the feature comprising the first metallic material and the second metallic material; and heating the substrate to a third temperature greater than the second temperature, causing a reflow of the second metallic material.Type: GrantFiled: September 15, 2020Date of Patent: December 13, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Lanlan Zhong, Fuhong Zhang, Gang Shen, Feng Chen, Rui Li, Xiangjin Xie, Tae Hong Ha, Xianmin Tang
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Publication number: 20220344275Abstract: Electronic devices and methods of forming electronic devices using a ruthenium or doped ruthenium liner and cap layer are described. A liner with a ruthenium layer and a cobalt layer is formed on a barrier layer. A conductive fill forms a second conductive line in contact with the first conductive line.Type: ApplicationFiled: July 6, 2022Publication date: October 27, 2022Applicant: Applied Materials, Inc.Inventors: Wenjing Xu, Feng Chen, Tae Hong Ha, Xianmin Tang, Lu Chen, Zhiyuan Wu
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Publication number: 20220336227Abstract: Methods for producing a reduced contact resistance for cobalt-titanium structures. In some embodiments, a method comprises depositing a titanium layer using a chemical vapor deposition (CVD) process, depositing a first cobalt layer on the titanium nitride layer using a physical vapor deposition (PVD) process, and depositing a second cobalt layer on the first cobalt layer using a CVD process.Type: ApplicationFiled: July 5, 2022Publication date: October 20, 2022Inventors: TAKASHI KURATOMI, AVGERINOS GELATOS, TAE HONG HA, XUESONG LU, SZUHENG HO, WEI LEI, MARK LEE, RAYMOND HUNG, XIANMIN TANG
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Publication number: 20220336223Abstract: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.Type: ApplicationFiled: June 22, 2022Publication date: October 20, 2022Applicant: Applied Materials, Inc.Inventors: Yu Lei, Xuesong Lu, Tae Hong Ha, Xianmin Tang, Andrew Nguyen, Tza-Jing Gung, Philip A. Kraus, Chung Nang Liu, Hui Sun, Yufei Hu
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Publication number: 20220328348Abstract: Methods of forming copper interconnects are described. A doped tantalum nitride layer formed on a copper layer on a substrate has a first amount of dopant. The doped tantalum nitride layer is exposed to a plasma comprising one or more of helium or neon to form a treated doped tantalum nitride layer with a decreased amount of dopant. Apparatus for performing the methods are also described.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Applicant: Applied Materials, Inc.Inventors: Rui Li, Xiangjin Xie, Tae Hong Ha, Xianmin Tang, Lu Chen
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Patent number: 11424132Abstract: Methods and apparatus for producing a reduced contact resistance for cobalt-titanium structures. In some embodiments, a method comprises depositing a titanium layer using a chemical vapor deposition (CVD) process, depositing a titanium nitride layer on the titanium layer using an atomic layer deposition (ALD) process, depositing a first cobalt layer on the titanium nitride layer using a physical vapor deposition (PVD) process, and depositing a second cobalt layer on the first cobalt layer using a CVD process.Type: GrantFiled: October 2, 2019Date of Patent: August 23, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Takashi Kuratomi, Avgerinos Gelatos, Tae Hong Ha, Xuesong Lu, Szuheng Ho, Wei Lei, Mark Lee, Raymond Hung, Xianmin Tang
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Patent number: 11417568Abstract: Methods and apparatus for selectively depositing a tungsten layer atop a dielectric surface.Type: GrantFiled: April 10, 2020Date of Patent: August 16, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Wei Lei, Yi Xu, Yu Lei, Tae Hong Ha, Raymond Hung, Shirish A. Pethe
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Patent number: 11410881Abstract: Methods of forming copper interconnects are described. A doped tantalum nitride layer formed on a copper layer on a substrate has a first amount of dopant. The doped tantalum nitride layer is exposed to a plasma comprising one or more of helium or neon to form a treated doped tantalum nitride layer with a decreased amount of dopant. Apparatus for performing the methods are also described.Type: GrantFiled: June 28, 2020Date of Patent: August 9, 2022Assignee: Applied Materials, Inc.Inventors: Rui Li, Xiangjin Xie, Tae Hong Ha, Xianmin Tang, Lu Chen
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Publication number: 20220231137Abstract: A contact stack of a semiconductor device comprises: a source/drain region; a metal silicide layer above the source/drain region; a metal cap layer directly on the metal silicide layer; and a conductor on the metal cap layer. A method comprises: depositing a metal silicide layer in a feature of a substrate; in the absence of an air break after the depositing of the metal silicide layer, preparing a metal cap layer directly on the metal silicide layer; and depositing a conductor on the metal cap layer.Type: ApplicationFiled: January 19, 2021Publication date: July 21, 2022Applicant: Applied Materials, Inc.Inventors: Bencherki Mebarki, Joung Joo Lee, Wenting Hou, Takashi Kuratomi, Avgerinos V. Gelatos, Jianxin Lei, Liqi Wu, Raymond Hoiman Hung, Tae Hong Ha, Xianmin Tang
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Publication number: 20220084882Abstract: Methods and apparatus for filling features on a substrate are provided herein. In some embodiments, a method of filling features on a substrate includes: depositing a first metallic material on the substrate and within a feature disposed in the substrate in a first process chamber via a chemical vapor deposition (CVD) process at a first temperature; depositing a second metallic material on the first metallic material in a second process chamber at a second temperature and at a first bias power to form a seed layer of the second metallic material; etching the seed layer in the second process chamber at a second bias power greater than the first bias power to form an intermix layer within the feature comprising the first metallic material and the second metallic material; and heating the substrate to a third temperature greater than the second temperature, causing a reflow of the second metallic material.Type: ApplicationFiled: September 15, 2020Publication date: March 17, 2022Inventors: Lanlan ZHONG, Fuhong ZHANG, Gang SHEN, Feng CHEN, Rui LI, Xiangjin XIE, Tae Hong HA, Xianmin TANG
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Patent number: 11270911Abstract: Described are methods for doping barrier layers such as tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), niobium (Nb), niobium nitride (NbN), manganese (Mn), manganese nitride (MnN), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), and molybdenum nitride (MoN), and the like. Dopants may include one or more of one or more of ruthenium (Ru), manganese (Mn), niobium (Nb), cobalt (Co), vanadium (V), copper (Cu), aluminum (Al), carbon (C), oxygen (O), silicon (Si), molybdenum (Mo), and the like. The doped barrier layer provides improved adhesion at a thickness of less than about 15 ?.Type: GrantFiled: May 6, 2020Date of Patent: March 8, 2022Assignee: Applied Materials Inc.Inventors: Lu Chen, Christina L. Engler, Gang Shen, Feng Chen, Tae Hong Ha, Xianmin Tang