Patents by Inventor Taehong KWON
Taehong KWON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145306Abstract: A method of manufacturing a semiconductor device is provided. The method includes: forming a first structure on a first wafer; forming a second structure on a second wafer including second chip regions and a second scribe lane region surrounding the second chip regions; separating first ones of the second chip regions in a central portion of the second wafer in a plan view by a first dicing process; bonding the first ones of the second chip regions with the first wafer; separating second ones of the second chip regions in an edge portion of the second wafer in a plan view by a second dicing process; bonding the second ones of the second chip regions with the first wafer, and separating the bonded first and second wafers by a third dicing process.Type: ApplicationFiled: August 21, 2023Publication date: May 2, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Gyosoo CHOO, Daeseok Byeon, Taehong Kwon
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Publication number: 20230399705Abstract: The present invention relates to isolated nucleic acid molecules, comprising a functional mammalian EGR-1 (early growth response protein 1) promoter region that is operatively linked to a gene encoding a fluorescent protein and controls expression of said gene. The present invention further relates to nucleic acid vectors, comprising said nucleic, cells comprising said nucleic acids or vectors, being capable of sensing and indicating fluid shear stress acting on themselves, and methods of generating the same. Furthermore, the present invention relates to methods of evaluating fluid shear stress acting on cells in real-time during the operation of a biotechnological device or system, methods of evaluating a biotechnological device or system with respect to fluid shear stress acting on cells caused by operation of said device or system, and methods of designing a biotechnological device or system, said methods using said cells.Type: ApplicationFiled: May 18, 2022Publication date: December 14, 2023Applicant: Sartorius Stedim Biotech GmbHInventors: Samin Akbari, Ann-Cathrin Leroux, Taehong Kwon, Christoph Zehe, David Pollard
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Patent number: 11513730Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data according to an M-bit data access scheme, where N is a natural number, and a first peripheral circuit for controlling the first memory cells and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data according to an M-bit data access scheme, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells and disposed below the second memory cell array, the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the caType: GrantFiled: June 4, 2020Date of Patent: November 29, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taehong Kwon, Daeseok Byeon, Chanho Kim, Taehyo Kim
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Patent number: 11302396Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.Type: GrantFiled: April 29, 2020Date of Patent: April 12, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Taehong Kwon, Youngsun Min, Daeseok Byeon, Kyunghwa Yun
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Patent number: 11289467Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.Type: GrantFiled: July 31, 2020Date of Patent: March 29, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Taehong Kwon, Youngsun Min, Daeseok Byeon, Kyunghwa Yun
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Patent number: 11282851Abstract: A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.Type: GrantFiled: October 24, 2019Date of Patent: March 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taehong Kwon, Chanho Kim, Daeseok Byeon, Pansuk Kwak, Chiweon Yoon
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Patent number: 11264082Abstract: A memory device comprises a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data, where N is a natural number, and a first peripheral circuit for controlling the first memory cells according to an N-bit data access scheme and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells according to an M-bit data access scheme and disposed below the second memory cell array, wherein the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and stoType: GrantFiled: September 17, 2020Date of Patent: March 1, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taehong Kwon, Daeseok Byeon, Chanho Kim, Taehyo Kim
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Patent number: 11237983Abstract: A memory device includes; a memory area including a first memory area including first memory cells storing N-bit data and a second memory area including second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.Type: GrantFiled: May 4, 2020Date of Patent: February 1, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Taehyo Kim, Daeseok Byeon, Taehong Kwon, Chanho Kim, Taeyun Lee
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Patent number: 11237955Abstract: A memory device comprises a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, wherein the memory cell region includes a first memory area having first memory cells storing N-bit data and a second memory area having second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and the peripheral circuit region includes a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.Type: GrantFiled: August 31, 2020Date of Patent: February 1, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Taehyo Kim, Daeseok Byeon, Taehong Kwon, Chanho Kim, Taeyun Lee
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Publication number: 20210124527Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data according to an M-bit data access scheme, where N is a natural number, and a first peripheral circuit for controlling the first memory cells and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data according to an M-bit data access scheme, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells and disposed below the second memory cell array, the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the caType: ApplicationFiled: June 4, 2020Publication date: April 29, 2021Inventors: Taehong Kwon, Daeseok Byeon, Chanho Kim, Taehyo Kim
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Publication number: 20210125659Abstract: A memory device comprises a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data, where N is a natural number, and a first peripheral circuit for controlling the first memory cells according to an N-bit data access scheme and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells according to an M-bit data access scheme and disposed below the second memory cell array, wherein the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and stoType: ApplicationFiled: September 17, 2020Publication date: April 29, 2021Inventors: Taehong Kwon, Daeseok Byeon, Chanho Kim, Taehyo Kim
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Publication number: 20210124693Abstract: A memory device includes; a memory area including a first memory area including first memory cells storing N-bit data and a second memory area including second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.Type: ApplicationFiled: May 4, 2020Publication date: April 29, 2021Inventors: TAEHYO KIM, DAESEOK BYEON, TAEHONG KWON, CHANHO KIM, TAEYUN LEE
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Publication number: 20210124679Abstract: A memory device comprises a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, wherein the memory cell region includes a first memory area having first memory cells storing N-bit data and a second memory area having second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and the peripheral circuit region includes a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.Type: ApplicationFiled: August 31, 2020Publication date: April 29, 2021Inventors: TAEHYO KIM, DAESEOK BYEON, TAEHONG KWON, CHANHO KIM, TAEYUN LEE
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Publication number: 20210065801Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.Type: ApplicationFiled: April 29, 2020Publication date: March 4, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Taehong KWON, Youngsun MIN, Daeseok BYEON, Kyunghwa YUN
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Publication number: 20210066281Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.Type: ApplicationFiled: July 31, 2020Publication date: March 4, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Taehong KWON, Youngsun MIN, Daeseok BYEON, Kyunghwa YUN
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Publication number: 20200321349Abstract: A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.Type: ApplicationFiled: October 24, 2019Publication date: October 8, 2020Inventors: Taehong KWON, Chanho KIM, Daeseok BYEON, Pansuk KWAK, Chiweon YOON
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Patent number: 10274504Abstract: Disclosed is a microcapsule encoded depending on the kind of a target substance included therein. The encoded microcapsule has a hydrophilic liquid core including the target substance and a hydrophobic shell surrounding the liquid core. The encoded microcapsule includes graphical codes introduced on the surface of the shell.Type: GrantFiled: October 28, 2013Date of Patent: April 30, 2019Assignee: QUANTAMATRIX INC.Inventors: Sunghoon Kwon, Younghoon Song, Taehong Kwon, Daewon Lee, Junhoi Kim
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Publication number: 20180188822Abstract: Various embodiments of the present invention relate to an electronic device having an auxiliary device that can be attached/detached. The disclosed device comprises: a first electronic device having a touch screen arranged thereon; and a second electronic device arranged to be forced against at least a partial area of a surface of the touch screen such that data is input to the touch screen by a pressing operation, wherein the second electronic device may comprise a keypad unit, which comprises an array of multiple key tops that are pressed, and a substrate, which operates the touch screen by means of pressing of the key tops.Type: ApplicationFiled: June 21, 2016Publication date: July 5, 2018Inventors: Jiyong KIM, Heonseok LEE, Hakyeol KIM, Jooyoung PARK, Taehong KWON
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Publication number: 20150119284Abstract: Disclosed is a microcapsule encoded depending on the kind of a target substance included therein. The encoded microcapsule has a hydrophilic liquid core including the target substance and a hydrophobic shell surrounding the liquid core. The encoded microcapsule includes graphical codes introduced on the surface of the shell.Type: ApplicationFiled: October 28, 2013Publication date: April 30, 2015Applicant: SNU R&DB FOUNDATIONInventors: Sunghoon KWON, Younghoon SONG, Taehong KWON, Daewon LEE, Junhoi KIM