Abstract: A memory device and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells disposed in an area where a plurality of word lines and a plurality of bit lines cross each other; a row decoder including row switches and configured to perform a selection operation on the plurality of word lines; a column decoder including column switches and configured to perform a selection operation on the plurality of bit lines; and a control logic configured to control, in a data read operation, a precharge operation to be performed on a selected word line in a word line precharge period, and to control a precharge operation to be performed on a selected bit line in a bit line precharge period; wherein a row switch connected to the selected word line is weakly turned on in the bit line precharge period.

Abstract: The memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row control circuit including a plurality of row switches corresponding to the word lines, a column control circuit including a plurality of column switches corresponding to the bit lines, and a control logic circuit configured to control pre-charge operations on a word line and a bit line of a selected memory cell and perform a control operation to float the word line and the bit line together after a pre-charge period during a data reading operation. One of the word line and the bit line is floated after the pre-charge period and the other one is pseudo-floated after the pre-charge period.

Abstract: A memory device includes a memory cell connected to a word line and a bit line, a row driver that drives the word line to a precharge level, a column driver that drives the bit line to a first target level, a sense amplifier that senses a first sensing level of the word line after the first target level is applied to the memory cell, and a read control circuit that controls the column driver so that a second target level different from the first target level is selectively applied to the memory cell depending on the first sensing level sensed by the sense amplifier.

Abstract: A variable resistance memory device includes memory cell stacks arranged in a first direction, the memory cell stacks including a first memory cell stack and a second memory cell stack. Each of the memory cell stacks includes a plurality of word lines, each word line of the plurality of word lines extending in a second direction intersecting the first direction and arranged in a third direction intersecting the first and second directions, and a memory cell connected to each of the plurality of word lines. Each of the memory cells includes a switching element and a variable resistance element. Each of the plurality of word lines of the first memory cell stack have a first thickness, in the first direction, of first word lines of the first memory cell stack is less than a second thickness, in the first direction, of each of the plurality of word lines of the second memory cell stack.

Abstract: A memory device includes a memory cell array including memory cells disposed at points at which word lines and bit lines intersect, a first decoder circuit determining a selected bit line and non-selected bit lines among the bit lines, a second decoder circuit determining a selected word line and non-selected word lines among the word lines, a current compensation circuit providing a current path drawing a compensation current from the selected word line to compensate for off currents flowing in the non-selected bit lines, a first sense amplifier comparing a voltage of the selected word line with a reference voltage and outputting an enable signal, and a second sense amplifier outputting a voltage difference between the voltage of the selected word line and the reference voltage during an operating time determined by the enable signal in a readout operation mode of the memory device.

Abstract: A memory device includes a plurality of memory cells each including a switching device and a storage device having a phase change material, a decoder circuit including a first bias circuit inputting a first bias voltage to a selected word line connected to a selected memory cell, a second bias circuit inputting a second bias voltage to a selected bit line, a first selection switching device and a first non-selection switching device connected between the first bias circuit and the selected word line, and a second selection switching device and a second non-selection switching device connected between an adjacent word line and the first bias circuit, a control logic sequentially turning off the first selection switching device and the second non-selection switching device, and a sense amplifier comparing a voltage of the selected word line with a reference voltage to determine data of a read operation.

Abstract: A memory device and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells disposed in an area where a plurality of word lines and a plurality of bit lines cross each other; a row decoder including row switches and configured to perform a selection operation on the plurality of word lines; a column decoder including column switches and configured to perform a selection operation on the plurality of bit lines; and a control logic configured to control, in a data read operation, a precharge operation to be performed on a selected word line in a word line precharge period, and to control a precharge operation to be performed on a selected bit line in a bit line precharge period; wherein a row switch connected to the selected word line is weakly turned on in the bit line precharge period.

Abstract: A memory device includes a plurality of memory cells each including a switching device and a storage device having a phase change material, a decoder circuit including a first bias circuit inputting a first bias voltage to a selected word line connected to a selected memory cell, a second bias circuit inputting a second bias voltage to a selected bit line, a first selection switching device and a first non-selection switching device connected between the first bias circuit and the selected word line, and a second selection switching device and a second non-selection switching device connected between an adjacent word line and the first bias circuit, a control logic sequentially turning off the first selection switching device and the second non-selection switching device, and a sense amplifier comparing a voltage of the selected word line with a reference voltage to determine data of a read operation.

Abstract: The memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row control circuit including a plurality of row switches corresponding to the word lines, a column control circuit including a plurality of column switches corresponding to the bit lines, and a control logic circuit configured to control pre-charge operations on a word line and a bit line of a selected memory cell and perform a control operation to float the word line and the bit line together after a pre-charge period during a data reading operation. One of the word line and the bit line is floated after the pre-charge period and the other one is pseudo-floated after the pre-charge period.

Abstract: A memory device includes a memory cell connected to a word line and a bit line, a row driver that drives the word line to a precharge level, a column driver that drives the bit line to a first target level, a sense amplifier that senses a first sensing level of the word line after the first target level is applied to the memory cell, and a read control circuit that controls the column driver so that a second target level different from the first target level is selectively applied to the memory cell depending on the first sensing level sensed by the sense amplifier.

Abstract: A memory device includes a memory cell array including memory cells disposed at points at which word lines and bit lines intersect, a first decoder circuit determining a selected bit line and non-selected bit lines among the bit lines, a second decoder circuit determining a selected word line and non-selected word lines among the word lines, a current compensation circuit providing a current path drawing a compensation current from the selected word line to compensate for off currents flowing in the non-selected bit lines, a first sense amplifier comparing a voltage of the selected word line with a reference voltage and outputting an enable signal, and a second sense amplifier outputting a voltage difference between the voltage of the selected word line and the reference voltage during an operating time determined by the enable signal in a readout operation mode of the memory device.

Abstract: A variable resistance memory device includes memory cell stacks arranged in a first direction, the memory cell stacks including a first memory cell stack and a second memory cell stack. Each of the memory cell stacks includes a plurality of word lines, each word line of the plurality of word lines extending in a second direction intersecting the first direction and arranged in a third direction intersecting the first and second directions, and a memory cell connected to each of the plurality of word lines. Each of the memory cells includes a switching element and a variable resistance element. Each of the plurality of word lines of the first memory cell stack have a first thickness, in the first direction, of first word lines of the first memory cell stack is less than a second thickness, in the first direction, of each of the plurality of word lines of the second memory cell stack.

Abstract: In an embodiment, an error detection and correction apparatus includes a positive edge triggered flip-flop that receives syndrome input based on a syndrome output a syndrome generator indicating whether or not input data includes an error, whereby the positive edge triggered flip-flop further provides a syndrome output to an error location decoder.

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

Abstract: Metal-oxide semiconductor (MOS) transistor offset-cancelling (OC), zero-sensing (ZS) dead zone, current-latched sense amplifiers (SAs) (CLSAs) (OCZS-SAs) for sensing differential voltages are provided. An OCZS-SA is configured to amplify received differential data and reference input voltages with a smaller sense amplifier offset voltage to provide larger sense margin between different storage states of memory bitcell(s). The OCZS-SA is configured to cancel out offset voltages of input and complement input transistors, and keep the input and complement input transistors in their activated state during sensing phases so that sensing is not performed in their “dead zones” when their gate-to-source voltage (Vgs) is below their respective threshold voltages.

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

Abstract: Non-volatile (NV)-content addressable memory (CAM) (NV-CAM) cells employing differential magnetic tunnel junction (MTJ) sensing for increased sense margin are disclosed. By the NV-CAM cells employing MTJ differential sensing, differential cell voltages can be generated for match and mismatch conditions in response to search operations. The differential cell voltages are amplified to provide a larger match line voltage differential for match and mismatch conditions, thus providing a larger sense margin between match and mismatch conditions. For example, a cross-coupled transistor sense amplifier employing positive feedback may be employed to amplify the differential cell voltages to provide a larger match line voltage differential for match and mismatch conditions. Providing NV-CAM cells that have a larger sense margin can mitigate sensing issues for increased search operation reliability.

Abstract: Systems and methods relate to operations on a magnetoresistive random access memory (MRAM) bit cell using a circuit configured in multiple phases. In a sensing circuit phase, the circuit configured to determine a first differential voltage between a data voltage across the bit cell and a reference voltage. In a pre-amplifying phase, the circuit is configured to pre-amplify the first differential voltage to generate a pre-amplified differential voltage, which does not have offset voltages that may arise due to process variations. In a sense amplifier phase, the circuit is configured to amplify the pre-amplified differential voltage in a latch. Generation of the pre-amplified differential voltage cancels offset voltages which may arise in the latch. In a write phase, the circuit is further configured to write a write data value to the MRAM bit cell.

Abstract: A method of sensing a data value stored at a memory cell according to a dual mode sensing scheme includes determining, at a sensing circuit, whether a resistance of a magnetic tunnel junction (MTJ) element is within a first range of resistance values, within a second range of resistance values, or within a third range of resistance values. The MTJ element is included in the memory cell. The method also includes determining the data value stored at the memory cell according to a first mode of operation if the resistance of the MTJ element is within the first range of resistance values or within the third range of resistance values. The method further includes determining the data value stored at the memory cell according to a second mode of operation if the resistance of the MTJ element is within the second range of resistance values.

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.