Abstract: The present technology relates to an electronic device. A memory device according to an embodiment includes a memory cell string including first memory cells included in a first channel area, second memory cells included in a second channel area, and dummy memory cells connected between the first memory cells and the second memory cells, a peripheral circuit configured to perform a program operation of storing data in the first and second memory cells, and a program operation controller configured to control the peripheral circuit to apply a first pass voltage to a dummy word line connected to the dummy memory cells during the program operation, apply a second pass voltage less than the first pass voltage to the dummy word line, and then apply a program voltage to a selected word line among a plurality of word lines connected to the first and second memory cells.

Abstract: The present technology relates to a semiconductor device. According to the present technology, a memory device capable of dividing and storing a plurality of data bits in a plurality of memory cells may include a plurality of memory cells each configured to have a state among a plurality of states, a code table generator configured to generate, based on a plurality of data bits, a code table indicating the plurality of states as code patterns formed by parts of the data bits, the parts corresponding to the respective memory cells, and an internal operation controller configured to divide and store a plurality of target data bits in the plurality of memory cells based on the code table during a program operation.

Abstract: The present technology relates to an electronic device. According to the present technology, a page buffer may include a bit line voltage control circuit, a latch and a reference voltage supply circuit. The bit line voltage control circuit may selectively connect a bit line and a sensing node. The latch may provide a latch signal corresponding to data. The reference voltage supply circuit may include a first PMOS transistor and a first NMOS transistor coupled in series between the sensing node and a ground voltage terminal, and apply a first reference voltage to the sensing node. The first PMOS transistor may be controlled according to the reference voltage control signal. The first NMOS transistor may be controlled by the latch signal.

Abstract: A method of operating a controller includes transmitting a program command to a memory device, receiving a message indicating that a program operation corresponding to the program command is failed from the memory device, and transmitting an erase command for performing an erase operation on a page corresponding to the program command to the memory device in response to the message.

Abstract: A memory device includes a controller that performs a program verification after a first program pulse is applied to the at least one non-volatile memory cell. The first program pulse is applied during a data program operation and the data program operation includes applying program pulses to program multi-bit data to the at least one non-volatile memory cell. The controller also determines a program mode for the at least one non-volatile memory cell based on a result of the program verification, and changes at least one of a level of a first control voltage based on the program mode. The first control voltage is applied to a drain select line coupled to the at least one non-volatile memory cell.

Abstract: A memory device includes a memory structure including at least one non-volatile memory cell capable of storing multi-bit data, and a control device configured to perform a program verification after a first program pulse is applied to the at least one non-volatile memory cell, determine a program mode for the at least one non-volatile memory cell based on a result of the program verification, and change a level of a pass voltage, applied to another non-volatile memory cell coupled to the at least one non-volatile memory cell, from a first level to a second level which is higher than the first level, or a setup time for changing a potential of a bit line coupled to the at least one non-volatile memory cell, according to the program mode.

Abstract: The present technology relates to an electronic device. A memory device according to an embodiment includes a memory cell string including first memory cells included in a first channel area, second memory cells included in a second channel area, and dummy memory cells connected between the first memory cells and the second memory cells, a peripheral circuit configured to perform a program operation of storing data in the first to second memory cells, and a program operation controller configured to control the peripheral circuit to apply a first pass voltage to a dummy word line connected to the dummy memory cells during the program operation, apply a second pass voltage less than the first pass voltage to the dummy word line, and then apply a program voltage to a selected word line among a plurality of word lines connected to the first and second memory cells.

Abstract: A memory device includes a memory structure including at least one non-volatile memory cell capable of storing multi-bit data, and a control device configured to perform a program verification after a first program pulse is applied to the at least one non-volatile memory cell, determine a program mode for the at least one non-volatile memory cell based on a result of the program verification, and change a level of a pass voltage, applied to another non-volatile memory cell coupled to the at least one non-volatile memory cell, from a first level to a second level which is higher than the first level, or a setup time for changing a potential of a bit line coupled to the at least one non-volatile memory cell, according to the program mode.

Abstract: A nonvolatile memory device comprising: a cell string comprising a plurality of memory cells, a bit line coupled to the cell string, and a page buffer suitable for precharging the bit line, a first sensing node and a second sensing node to a preset level in a first period, and double-sensing the bit line through the first and second sensing nodes in a second period, wherein the page buffer comprises: a first coupling unit suitable for coupling the bit line and the first sensing node, a second coupling unit suitable for coupling the first and second sensing nodes, and controlling the first and second sensing nodes to have a voltage level interval according to a preset ratio in the second period, a first and second latch units suitable for latching a logic levels corresponding to a voltage levels of the first and second sensing nodes, respectively.

Abstract: A memory device includes a controller that performs a program verification after a first program pulse is applied to the at least one non-volatile memory cell. The first program pulse is applied during a data program operation and the data program operation includes applying program pulses to program multi-bit data to the at least one non-volatile memory cell. The controller also determines a program mode for the at least one non-volatile memory cell based on a result of the program verification, and changes at least one of a level of a first control voltage based on the program mode. The first control voltage is applied to a drain select line coupled to the at least one non-volatile memory cell.

Abstract: Provided is a memory device. The memory device may include a voltage code controller configured to generate a voltage code that generates a program voltage and pass voltages based on a number of times a program loop is performed, and a voltage generator configured to generate the program voltage and the pass voltages in response to the voltage code, transmit the program voltage to a selected word line, and transmit the pass voltages to unselected word lines, wherein the voltage generator is configured to sequentially increase the pass voltage that is applied to the unselected word lines in order of proximity to the selected word line as the number of times a program loop is performed increases.

Abstract: A nonvolatile memory device comprising: a cell string comprising a plurality of memory cells, a bit line coupled to the cell string, and a page buffer suitable for precharging the bit line, a first sensing node and a second sensing node to a preset level in a first period, and double-sensing the bit line through the first and second sensing nodes in a second period, wherein the page buffer comprises: a first coupling unit suitable for coupling the bit line and the first sensing node, a second coupling unit suitable for coupling the first and second sensing nodes, and controlling the first and second sensing nodes to have a voltage level interval according to a preset ratio in the second period, a first and second latch units suitable for latching a logic levels corresponding to a voltage levels of the first and second sensing nodes, respectively.

Abstract: Provided is a memory device. The memory device may include a voltage code controller configured to generate a voltage code that generates a program voltage and pass voltages based on a number of times a program loop is performed, and a voltage generator configured to generate the program voltage and the pass voltages in response to the voltage code, transmit the program voltage to a selected word line, and transmit the pass voltages to unselected word lines, wherein the voltage generator is configured to sequentially increase the pass voltage that is applied to the unselected word lines in order of proximity to the selected word line as the number of times a program loop is performed increases.

Abstract: The present invention relates to a skin preparation composition for external use having excellent antiseptic ability without using chemical antiseptics. More particularly, the present invention relates to a skin preparation composition for external use, comprising: glyceryl undecylenate having excellent antiseptic ability; and one or more mixtures of ethylhexylglycerin, glyceryl caprylate, p-anisic acid and a citrus mixed extract, thus improving antiseptic ability through the increased effects of antiseptic abilities of those materials.

Abstract: The present invention relates to a phytospingosine derivative generated by a condensation reaction of phytospingosine and maltose or lactose, which is an aldose-based disaccharide, and to a composition containing the same. The phytospingosine derivative of the present invention has high solubility in water compared with phytospingosine, is easy to formulate since the stabilization problem in a solution is solved, and maintains or further enhances the antibacterial effect of phytospingosine.

Abstract: A vehicle side-rear warning device includes a camera which records a side-rear of a vehicle, a sensor, a monitor which displays an image recorded by the camera, and a side-rear warning system control unit. An image signal recorded by the camera and a signal sensed by the sensor are input to the side-rear warning system control unit, which determines whether an object is located at a predetermined area of the side-rear of the vehicle based on the input image signal and the input signal sensed by the sensor. When the object is located within a predetermined area of the side-rear of the vehicle, the side-rear warning system control unit outputs a warning signal. The monitor displays the image signal received from the side-rear warning system control unit.

Abstract: The present invention relates to a phytospingosine derivative generated by a condensation reaction of phytospingosine and maltose or lactose, which is an aldose-based disaccharide, and to a composition containing the same. The phytospingosine derivative of the present invention has high solubility in water compared with phytospingosine, is easy to formulate since the stabilization problem in a solution is solved, and maintains or further enhances the antibacterial effect of phytospingosine.

Abstract: Disclosed are novel Lactobacillus plantarum strains as well as a composition containing the novel Lactobacillus plantarum strains or a culture thereof.

Abstract: Disclosed are novel Lactobacillus plantarum strains as well as a composition containing the novel Lactobacillus plantarum strains or a culture thereof.

Abstract: Disclosed are novel Lactobacillus plantarum strains as well as a composition containing the novel Lactobacillus plantarum strains or a culture thereof.