Abstract: The present invention relates to technology for fabricating a gallium nitride substrate using an ion implantation process to which a self-separation technique is applied. According to the present invention, a method of fabricating a gallium nitride substrate may include a step of forming a first gallium nitride layer on a substrate, a step of implanting hydrogen ions into the first gallium nitride layer to form a separation layer, a step of grinding the edges of the substrate, the first gallium nitride layer, and the separation layer, a step of forming a second gallium nitride layer on the first gallium nitride layer having a ground edge, and a step of self-separating the second gallium nitride layer from the first gallium nitride layer having a ground edge.

Abstract: A memory device contains lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic antiferromagnetic layers, and an upper electrode, which are formed on a substrate in a laminated manner. In the memory device, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.

Abstract: The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.

Abstract: A memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic antiferromagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. The lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.

Abstract: The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.

Abstract: Disclosed is a method of fabricating a gallium nitride substrate using a plurality of ion implantation processes.

Abstract: Disclosed is a method of fabricating a gallium nitride substrate using a plurality of ion implantation processes.

Abstract: Disclosed a method of fabricating a gallium nitride substrate using hydride vapor phase epitaxy (HVPE), including a step of injecting ammonia (NH3) gas to perform first surface treatment on a sapphire substrate; a step of injecting ammonia gas and hydrogen chloride (HCl) gas to form a buffer layer on the sapphire substrate; a step of injecting ammonia gas to perform second surface treatment on the sapphire substrate; and a step of allowing gallium nitride (GaN) to grow on the sapphire substrate while lowering the flow rate ratio of ammonia gas to hydrogen chloride gas stepwise.

Abstract: Disclosed a method of fabricating a gallium nitride substrate using hydride vapor phase epitaxy (HVPE), including a step of injecting ammonia (NH3) gas to perform first surface treatment on a sapphire substrate; a step of injecting ammonia gas and hydrogen chloride (HCl) gas to form a buffer layer on the sapphire substrate; a step of injecting ammonia gas to perform second surface treatment on the sapphire substrate; and a step of allowing gallium nitride (GaN) to grow on the sapphire substrate while lowering the flow rate ratio of ammonia gas to hydrogen chloride gas stepwise.

Abstract: Disclosed is a method of fabricating a gallium nitride substrate using nanoparticles with a core-shell structure. A method of fabricating a gallium nitride substrate using nanoparticles with a core-shell structure according to an embodiment of the present disclosure includes a step of coating nanoparticles with a core-shell structure on a temporary substrate to form at least one nanoparticle layer; a step of allowing a pit gallium nitride (pit GaN) layer to grow on the temporary substrate; a step of allowing a mirror GaN layer (mirror GaN) to grow on the pit GaN layer; and a step of separating the temporary substrate, wherein each of the nanoparticles with a core-shell structure includes a core and an ionic polymer shell coated on a surface of the core surface.

Abstract: The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.

Abstract: The present invention provides a memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic exchange diamagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. According to the present invention, the lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.

Abstract: Provided are a solar cell a solar cell having high light absorbance and power conversion efficiency and a method for producing the solar cell. The solar cell includes a substrate, a first electrode disposed on the substrate, a photoactive layer disposed on the first electrode, and a second electrode disposed on the photoactive layer. The photoactive layer includes an electron acceptor and at least two electron donors.

Abstract: Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.

Abstract: Provided are a solar cell a solar cell having high light absorbance and power conversion efficiency and a method for producing the solar cell. The solar cell includes a substrate, a first electrode disposed on the substrate, a photoactive layer disposed on the first electrode, and a second electrode disposed on the photoactive layer. The photoactive layer includes an electron acceptor and at least two electron donors.

Abstract: The present invention provides a solar cell and manufacturing method thereof. The solar cell according to the present invention comprises: first and second electrodes, at least one of which has light transmitting properties; two or more photoelectric conversion layers positioned between the first and second electrodes; and a transflective conductive layer positioned between the photoelectric conversion layers. Further, tunneling layers are also provided between the photoelectric conversion layers and the transflective conductive layer. The efficiency of the solar cell can be improved, as compared with the prior art, by providing tunneling layers and a transflective conductive layer in this way.

Abstract: Provided is a capacitorless memory device. The device includes a semiconductor substrate, an insulating layer disposed on the semiconductor substrate, a storage region disposed on a partial region of the insulating layer, a channel region disposed on the storage region to provide a valence band energy offset between the channel region and the storage region, a gate insulating layer and a gate electrode sequentially disposed on the channel region, and source and drain regions connected to the channel region and disposed at both sides of the gate electrode. A storage region having different valence band energy from a channel region is disposed under the channel region unit so that charges trapped in the storage region unit cannot be easily drained. Thus, a charge retention time may be increased to improve data storage capability.

Abstract: Semiconductor wafers are packed by providing a carrying device that holds one or more semiconductor wafers. The carrying device is inserted into a packing bag and the packing bag is molded using at least a portion of the external form of the carrying device as a guide such that a portion of the packing bag substantially conforms to the portion of the external form of the carrying device. Thus, wafers may be packaged without using a vacuum while still inhibiting contamination from particles and the formation of haze on the surface of the wafers.