Patents by Inventor Tae Hun YI

Tae Hun YI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor package including stacked semiconductor chips and method for fabricating the semiconductor package
    Patent number: 11569216
    Abstract: A semiconductor package includes: a second semiconductor chip including a second through electrode that penetrates a second body portion and a second connection electrode that is connected to one end of the second through electrode; a first semiconductor chip stack disposed over the second semiconductor chip and including a plurality of first semiconductor chips, each of the plurality of first semiconductor chips includes a first through electrode and a first connection electrode connected to one end of the first through electrode; a molding layer; a third semiconductor chip disposed over the molding layer and the first semiconductor chip stack; and an external connection electrode electrically connected to an other end of the second through electrode, wherein, the second semiconductor chip and the plurality of first semiconductor chips are electrically connected through the second through electrode, the second connection electrode, the first through electrodes, and the first connection electrodes.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: January 31, 2023
    Assignee: SK hynix Inc.
    Inventors: Wan Choon Park, Gyu Jei Lee, Jong Hoon Kim, Tae Hun Yi
  • SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS AND METHOD FOR FABRICATING THE SEMICONDUCTOR PACKAGE
    Publication number: 20220077127
    Abstract: A semiconductor package includes: a second semiconductor chip including a second through electrode that penetrates a second body portion and a second connection electrode that is connected to one end of the second through electrode; a first semiconductor chip stack disposed over the second semiconductor chip and including a plurality of first semiconductor chips, each of the plurality of first semiconductor chips includes a first through electrode and a first connection electrode connected to one end of the first through electrode; a molding layer; a third semiconductor chip disposed over the molding layer and the first semiconductor chip stack; and an external connection electrode electrically connected to an other end of the second through electrode, wherein, the second semiconductor chip and the plurality of first semiconductor chips are electrically connected through the second through electrode, the second connection electrode, the first through electrodes, and the first connection electrodes.
    Type: Application
    Filed: February 2, 2021
    Publication date: March 10, 2022
    Applicant: SK hynix Inc.
    Inventors: Wan Choon PARK, Gyu Jei LEE, Jong Hoon KIM, Tae Hun YI