Abstract: Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.

Abstract: The proposed invention is about an improved method for serial-in and serial-out transceiver applications. The proposed system includes a dual loop phase locked loop (PLL) architecture having a PLL and a phase rotator (PR)-based delay locked loop (DLL). An advantage of this architecture is that a single PLL offers decoupled bandwidths; a wide jitter-tolerance (JTOL) bandwidth for receiving data and a narrow jitter transfer (JTRAN) bandwidth for the data transmission. Thus, the amount of jitter at the output can be substantially reduced relative to the input while offering sufficient jitter tracking bandwidth. Also, this architecture is suitable for low-power applications since a phase shifter in the data path, which is one of the most power-hungry blocks in conventional DPLL designs, is not required.

Abstract: Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (EOM) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed. The multiphase multiplexer is composed of parallelized open-drain NAND gates. In subrate transmitter architecture, the phase mismatch among multiphase clock signals degrades jitter performance significantly and is a critical bottleneck for its widespread use despite low power consumption. In order to overcome such mismatch problem, an area-and-power-efficient phase interpolator based waveform synthesizing scheme is developed.

Abstract: Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device converts a sequentially-changing step voltage into a current so as to provide a write current, and minimizes the influence of a threshold voltage variation caused by fabrication deviation, such that it can be stably operated. The semiconductor memory device includes a current driver. The current driver includes a step voltage provider configured to provide a step control voltage sequentially changing in response to a pulse control signal, a control current provider configured to provide a control current in response to the step control voltage, and a write driver configured to provide a write current capable of writing data in a memory cell in response to the control current.

Abstract: A phase change memory apparatus includes: a plurality of sub blocks; a latch block connected in common with the sub blocks through a read bus and configured to latch data from one of the sub blocks; and a comparator connected in common with the sub blocks to receive data from a write bus, and configured to compare data of the latch block with the data of the write bus to generate a comparison signal, which is effective in improving areal efficiency by sharing the latch block among the sub blocks in the unit mat.

Abstract: A semiconductor memory apparatus includes a memory cell, a data transfer unit configured to adjust an access to the memory cell according to a voltage level of a selection signal, a selection signal output unit configured to output the selection signal having a first control voltage level in a data write mode and a second control voltage level in a data read mode. A data detection unit may also be configured to detect a voltage formed by a sensing current supplied to the memory cell through the data transfer unit in the data read mode, and output read data according to the detection result, wherein the second control voltage level is lower than the first control voltage level.

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device converts a sequentially-changing step voltage into a current so as to provide a write current, and minimizes the influence of a threshold voltage variation caused by fabrication deviation, such that it can be stably operated. The semiconductor memory device includes a current driver. The current driver includes a step voltage provider configured to provide a step control voltage sequentially changing in response to a pulse control signal, a control current provider configured to provide a control current in response to the step control voltage, and a write driver configured to provide a write current capable of writing data in a memory cell in response to the control current.

Abstract: A nonvolatile memory device includes a data sense amplifier configured to supply a data detection current to a memory cell and detect a data detection voltage having a voltage level corresponding to a resistance of the memory cell, a first switching element configured to selectively transfer the data detection current to the memory cell, and a second switching element configured to be turned on simultaneously with the first switching element to selectively transfer the data detection current to the memory cell. The first switching element and the second switching element have a complementary voltage transfer characteristic.

Abstract: A test circuit transfers data, which is generated by current supplied from an external source, to a memory cell in response to a test mode signal.

Abstract: A semiconductor memory apparatus includes a memory cell, a data transfer unit configured to adjust an access to the memory cell according to a voltage level of a selection signal, a selection signal output unit configured to output the selection signal having a first control voltage level in a data write mode and a second control voltage level in a data read mode. A data detection unit may also be configured to detect a voltage formed by a sensing current supplied to the memory cell through the data transfer unit in the data read mode, and output read data according to the detection result, wherein the second control voltage level is lower than the first control voltage level.

Abstract: An integrated circuit substrate includes an integrated circuit chip having a plurality of electrically conductive pads on a surface thereof and a printed circuit board mounted to the integrated circuit chip. The printed circuit board includes an alternating arrangement of first and second electrically conductive bond fingers. These first and second bond fingers are elevated at first and second different heights, respectively, relative to the plurality of electrically conductive pads. The printed circuit board also includes a first plurality of electrically insulating pedestals supporting respective ones of the first electrically conductive bond fingers at elevated heights relative to the second electrically conductive bond fingers. First and second pluralities of electrical interconnects (e.g., wires, beam leads) are also provided.

Abstract: A nonvolatile memory device includes a plurality of programming current driving units configured to supply memory cells with a programming current corresponding to a write data, a common programming current controlling unit configured to generate a common control voltage for controlling the programming current and a switching unit configured to transfer the common control voltage to the programming current driving unit selected among the plurality of programming current driving units by a plurality of driving selection signals.

Abstract: A phase change memory apparatus includes: a plurality of sub blocks; a latch block connected in common with the sub blocks through a read bus and configured to latch data from one of the sub blocks; and a comparator connected in common with the sub blocks to receive data from a write bus, and configured to compare data of the latch block with the data of the write bus to generate a comparison signal, which is effective in improving areal efficiency by sharing the latch block among the sub blocks in the unit mat.

Abstract: A test circuit transfers data, which is generated by current supplied from an external source, to a memory cell in response to a test mode signal.

Abstract: A nonvolatile memory device includes a data sense amplifier configured to supply a data detection current to a memory cell and detect a data detection voltage having a voltage level corresponding to a resistance of the memory cell, a first switching element configured to selectively transfer the data detection current to the memory cell, and a second switching element configured to be turned on simultaneously with the first switching element to selectively transfer the data detection current to the memory cell. The first switching element and the second switching element have a complementary voltage transfer characteristic.

Abstract: A nonvolatile memory device includes a plurality of programming current driving units configured to supply memory cells with a programming current corresponding to a write data, a common programming current controlling unit configured to generate a common control voltage for controlling the programming current and a switching unit configured to transfer the common control voltage to the programming current driving unit selected among the plurality of programming current driving units by a plurality of driving selection signals.