Patents by Inventor Tae-Hwan Hwang

Tae-Hwan Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200197909
    Abstract: The present invention relates to a method for preparing superabsorbent polymer that has not only excellent permeability and absorption speed, but also minimized absorbency under pressure decrease rate, and superabsorbent polymer prepared thereby.
    Type: Application
    Filed: March 4, 2020
    Publication date: June 25, 2020
    Applicant: LG Chem, Ltd.
    Inventors: Min Ho Hwang, Hye Mi Nam, Sang Gi Lee, Soo Jin Lee, Tae Hwan Jang
  • Patent number: 10665930
    Abstract: The present invention relates to a tile structure of a shape-adaptive phased array antenna, and more specifically to a tile structure of a shape-adaptive phased array antenna configured to improve drag and low-observable properties of an airplane, and minimize a structural interference between adjacent tiles of the phased array antenna.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: May 26, 2020
    Assignee: AGENCY FOR DEFENSE DEVELOPMENT
    Inventors: Tae Hwan Joo, Jong Woo Seo, Ji Ho Ryu, Ki Chul Kim, Chan Ho Hwang, Min Sung Kim, Cheol Hoon Lee
  • Patent number: 10654959
    Abstract: The present invention provides a method for preparing a superabsorbent polymer, the method comprising the steps of: forming a function gel polymer by cross-linked polymerization of a monomer mixture under the presence of an internal cross-linking agent, the monomer mixture including a water-soluble ethylene-based unsaturated monomer having an acid group at least part of which is neutralized, a carbonate, a volatile organic solvent, a surfactant, and a bubble promoting agent; forming a base resin powder by drying, grinding, and classifying the function gel polymer; and forming a surface cross-linked layer by additional cross-linking of the surface of the base resin powder under the presence of a surface cross-linking agent. The method for preparing a superabsorbent polymer may provide a superabsorbent polymer which has a porous structure, thereby exhibiting an excellent absorption rate while exhibiting excellent gel strength.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: May 19, 2020
    Assignee: LG Chem, Ltd.
    Inventors: Soo Jin Lee, Hye Mi Nam, Sang Gi Lee, Min Ho Hwang, Tae Hwan Jang
  • Patent number: 10653812
    Abstract: Provided is a method of preparing a superabsorbent polymer which exhibits more improved liquid permeability and absorption rate while maintaining excellent absorption performance. The method of preparing the superabsorbent polymer may include the steps of: performing crosslinking polymerization of water-soluble ethylene-based unsaturated monomers having acidic groups which are at least partially neutralized in the presence of an internal crosslinking agent to form a water-containing gel polymer including a crosslinked polymer; drying, pulverizing, and size-sorting the water-containing gel polymer to form a base polymer powder; performing surface-crosslinking of the base polymer powder using a surface-crosslinking solution including one or more surface-crosslinking agents in the presence of first alumina particles; and adding second alumina particles to the surface-crosslinked base polymer powder and then mixing them with each other.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: May 19, 2020
    Assignee: LG Chem, Ltd.
    Inventors: Min Ho Hwang, Hye Mi Nam, Sang Gi Lee, Soo Jin Lee, Tae Hwan Jang
  • Patent number: 10650958
    Abstract: A coil electronic component includes a body portion and an external electrode. The body portion includes a coil layer and a reinforcing layer disposed on at least one of an upper portion and a lower portion of the coil layer. The external electrode is disposed on an outer surface of the body portion. The coil layer includes an insulating layer, a coil pattern, and a first conductivity type via penetrating through the insulating layer to be connected to the coil pattern, and the reinforcing layer has a higher degree of rigidity than the insulating layer.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Hui Jo, Han Lee, Mi Sun Hwang, Jeong Min Cho, Myung Sam Kang, Seok Hwan Ahn, Tae Hoon Kim
  • Publication number: 20200135636
    Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.
    Type: Application
    Filed: June 25, 2019
    Publication date: April 30, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuek Jae LEE, Ji Hoon KIM, Tae Hun KIM, Ji Seok HONG, Ji Hwan HWANG
  • Publication number: 20200135683
    Abstract: A semiconductor package includes a first semiconductor chip including a body portion, a first bonding layer disposed on a first surface of the body portion, and through vias passing through at least a portion of the body portion; and a first redistribution portion disposed in the first semiconductor chip to be connected to the first semiconductor chip through the first bonding layer, the first redistribution portion including first redistribution layers electrically connected to the first semiconductor chip, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer connected to the first bonding layer. The first bonding layer and the second bonding layer include first and metal pads disposed to correspond to each other and bonded to each other, respectively, and a first insulating layer and a second bonding insulating layer surrounding the first metal pads and the second metal pads, respectively.
    Type: Application
    Filed: July 15, 2019
    Publication date: April 30, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun Chul Kim, Tae Hun Kim, Ji Hwan Hwang
  • Publication number: 20200135684
    Abstract: A semiconductor package includes a first semiconductor chip including a first bonding layer, on one surface, and a chip structure stacked on the first semiconductor chip and including a second bonding layer on a surface facing the first semiconductor chip and a plurality of second semiconductor chips. The plurality of second semiconductor chips includes a chip area and a scribe area outside of the chip area, respectively, the plurality of second semiconductor chips being connected to each other by the scribe area in the chip structure. The first and second bonding layers include first and second metal pads disposed to correspond to each other and bonded to each other, respectively and first and second bonding insulating layers surrounding the first and second metal pads, respectively.
    Type: Application
    Filed: July 19, 2019
    Publication date: April 30, 2020
    Inventors: Sun Chul KIM, Tae Hun KIM, Ji Hwan HWANG
  • Publication number: 20200135698
    Abstract: A die stack structure may include a base die having base contact pads insulated by a base protection patterns and a flat side surface, a die stack bonded to the base die and having a plurality of component dies on the base die such that each of the component dies includes component contact pads insulated by a corresponding component protection pattern, and a residual mold unevenly arranged on a side surface of the die stack such that the component dies are attached to each other by the residual mold.
    Type: Application
    Filed: August 6, 2019
    Publication date: April 30, 2020
    Inventors: Ji-Seok HONG, Ji-Hoon KIM, Tae-Hun KIM, Hyuek-Jae LEE, Ji-Hwan HWANG
  • Publication number: 20200135594
    Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.
    Type: Application
    Filed: July 11, 2019
    Publication date: April 30, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuek Jae LEE, Tae Hun KIM, Ji Hwan HWANG, Ji Hoon KIM, Ji Seok HONG
  • Publication number: 20200135699
    Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 30, 2020
    Inventors: Ji Hwan HWANG, Ji Hoon KIM, Ji Seok HONG, Tae Hun KIM, Hyuek Jae LEE
  • Patent number: 10632451
    Abstract: The present invention relates to a method for preparing superabsorbent polymer that has not only excellent permeability and absorption speed, but also minimized absorbency under pressure decrease rate, and superabsorbent polymer prepared thereby.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: April 28, 2020
    Assignee: LG Chem, Ltd.
    Inventors: Min Ho Hwang, Hye Mi Nam, Sang Gi Lee, Soo Jin Lee, Tae Hwan Jang
  • Patent number: 10622335
    Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of tire plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Hwan Hwang, Sang-Sick Park, Tae-Hong Min, Geol Nam
  • Publication number: 20200098719
    Abstract: A semiconductor package includes a first semiconductor chip having a first through substrate via (TSV), a second semiconductor chip stacked on the first semiconductor chip and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes a second through substrate via connected to the first through substrate via. A side surface of the first adhesive layer is recessed from side surfaces of the first and second semiconductor chips.
    Type: Application
    Filed: June 12, 2019
    Publication date: March 26, 2020
    Inventors: Sang Sick PARK, Un Byoung KANG, Tae Hong MIN, Teak Hoon LEE, Ji Hwan HWANG
  • Patent number: 10574599
    Abstract: A contents providing method is implemented with a computer including at least one processor and a memory. The method includes: registering contents by matching time information with data received from a first user terminal, and storing the data in association with the time information; receiving a request for access to the registered contents; establishing a conversation interface with a messenger account related to the registered contents in response to the request for access; and reproducing the registered contents as a real-time conversation by providing the data through the conversation interface in an order corresponding to the time information.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: February 25, 2020
    Assignee: LINE Corporation
    Inventors: Tae Hwan Hwang, Seok Chan Lee
  • Publication number: 20200057185
    Abstract: An optical member includes a light guide plate, a first low refractive layer, a wavelength conversion layer, and a passivation layer. The first low refractive layer is disposed on the light guide plate. A refractive index of the first low refractive layer is smaller than a refractive index of the light guide plate. The wavelength conversion layer is disposed on the first low refractive layer. The passivation layer is disposed on the wavelength conversion layer. The passivation layer covers a side surface of the wavelength conversion layer and a side surface of the first low refractive layer on at least one side.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: Seong Yong Hwang, Jin Ho Park, Tae Gil Kang, Hyuk Hwan Kim, Sang Won Lee, Jae Jin Choi
  • Publication number: 20200044324
    Abstract: The present invention relates to a tile structure of a shape-adaptive phased array antenna, and more specifically to a tile structure of a shape-adaptive phased array antenna configured to improve drag and low-observable properties of an airplane, and minimize a structural interference between adjacent tiles of the phased array antenna.
    Type: Application
    Filed: August 9, 2018
    Publication date: February 6, 2020
    Inventors: Tae Hwan JOO, Jong Woo SEO, Ji Ho RYU, Ki Chul KIM, Chan Ho HWANG, Min Sung KIM, Cheol Hoon LEE
  • Publication number: 20190339559
    Abstract: Provided is a display apparatus including a bezel that is improved to prevent electrostatic discharge (ESD). The display apparatus includes a display panel on which an image is to be displayed, a chassis arranged at a rear side of the display panel and including a conductive material, a bezel configured to support the display panel and including a non-conductive material, and an adhesive including a conductive material and coated on an inner side surface of the bezel such that static electricity is guided away from being discharged toward an inside of the display apparatus.
    Type: Application
    Filed: May 2, 2019
    Publication date: November 7, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung Hwan KIM, Do Wan KIM, Myeong Gil KIM, Min Chul KIM, Boum Sik KIM, Tae Youn YOON, Sang Min LEE, Hyun Jun JUNG, Hye Ryung HWANG
  • Patent number: 10456224
    Abstract: The present invention relates to a method of guiding a dental implant treatment plan, a device and a recording medium therefore. The method of guiding a dental implant treatment plan according to the invention, by providing a guide to the area where the implant object is to be placed, the effects of reducing the complexity of the implant plan and decreasing procedure deviations depending on individual to individual can be achieved.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: October 29, 2019
    Assignee: OSSTEMIMPLANT CO., LTD.
    Inventors: Kyoo Ok Choi, Tae Hwan Kim, Seung Yong Hwang, Seong Yun Lee
  • Publication number: 20190324854
    Abstract: A memory device includes: a first memory bank and a second memory bank; a control logic configured to receive a command and control an internal operation of the memory device; and an error correction code (ECC) circuit configured to retain in a latch circuit first read data read from the first memory bank in response to a first masked write (MWR) command for the first memory bank based on a latch control signal from the control logic, generate a first parity from data in which the first read data retained in the latch circuit is merged with first write data corresponding to the first MWR command in response to a first write control signal received from the control logic, and control an ECC operation to retain in the latch circuit second read data read from the second memory bank based on the latch control signal.
    Type: Application
    Filed: April 19, 2019
    Publication date: October 24, 2019
    Inventors: Jung-hwan Park, Tae-young Oh, Hyung-joon Chi, Kyung-soo Ha, Hyong-ryol Hwang