Abstract: The present disclosure relates to a method for carrying out dose delivery quality assurance for high-precision radiation treatment, in which parameters affecting a pass rate of dose delivery quality assurance can be derived through regression analysis, which is a known statistical analysis method, and a pass rate prediction model capable of predicting each parameter and the pass rate of dose delivery quality assurance can be derived, and accordingly, it can be predicted in advance whether dose delivery quality assurance will be passed according to the parameters through the above prediction model, without repeatedly carrying out dose delivery quality assurance according to a patient's treatment plan, and as a result, the efficiency of dose delivery quality assurance can be enhanced, and the time or capacity required for such quality assurance is reduced, such that radiation treatment for an actual patient can be quickly and precisely carried out.

Abstract: The present invention discloses a system and method for redesigning treatment prescriptions according to evaluation of treatment effectiveness. In the present invention, when the system receives the treatment prescriptions from the medical staff terminal, sets the treatment device according to the treatment prescriptions, and delivers the treatment device to the patient, the patient performs treatment by himself using the treatment device at home. When the treatment is finished, the patient terminal transmits the treatment history information, the treatment image obtained by photographing the process of self-treatment, and the questionnaire replies to the system. The system calculates compliance from the treatment history information, evaluates the treatment motor/cognitive/emotional functions from the questionnaire reply, and then provides them to the medical staff terminal together with the questionnaire replies, and allows the medical staff to evaluate effect of the treatment prescriptions.

Abstract: Disclosed are a method for manufacturing a homojunction or heterojunction bipolar device and a structure of the bipolar device manufactured by the method.

Abstract: Disclosed are a method for forming a base layer by epitaxial growth technology of a heterojunction bipolar device and a structure of the bipolar device manufactured by the method.

Abstract: The present invention is related to a bipolar transistor in which the in-situ doped epitaxial Si or SiGe base layer is used instead of using an ion-implanted Si base, in order to achieve higher cutoff frequency. The SiGe base having the narrower energy bandgap than the Si emitter allows to enhance the current gain, the cutoff frequency(fT), and the maximum oscillation frequency (fmax). The narrow bandgap SiGe base also allows to have higher base doping concentration. As a result, the intrinsic base resistance is lowered and the noise figure is thus lowered. Parasitic base resistance is also minimized by using a metallic silicide base ohmic electrode. The present invention is focused on low cost, high repeatability and reliability by simplifying the manufacturing process step.

Abstract: Disclosed are a method for forming a base layer by epitaxial growth technology of a heterojunction bipolar device and a structure of the bipolar device manufactured by the method.

Abstract: Disclosed are a method for manufacturing a homojunction or heterojunction bipolar device and a structure of the bipolar device manufactured by the method.

Abstract: The present invention is related to a bipolar transistor in which the in-situ doped epitaxial Si or SiGe base layer is used instead of using an ion-implanted Si base, in order to achieve higher cutoff frequency. The SiGe base having the narrower energy bandgap than the Si emitter allows to enhance the current gain, the cutoff frequency (fT), and the maximum oscillation frequency (fmax). The narrow bandgap SiGe base also allows to have higher base doping concentration. As a result, the intrinsic base resistance is lowered and the noise figure is thus lowered. Parasitic base resistance is also minimized by using a metallic silicide base ohmic electrode. The present invention is focused on low cost, high repeatability and reliability by simplifying the manufacturing process step.

Abstract: The present invention is related to a bipolar transistor in which the in-situ doped epitaxial Si or SiGe base layer is used instead of using an ion-implanted Si base, in order to achieve higher cutoff frequency. The SiGe base having the narrower energy bandgap than the Si emitter allows to enhance the current gain, the cutoff frequency (fT), and the maximum oscillation frequency (fmax). The narrow bandgap SiGe base also allows to have higher base doping concentration. As a result, the intrinsic base resistance is lowered and the noise figure is thus lowered. Parasitic base resistance is also minimized by using a metallic silicide base ohmic electrode. The present invention is focused on low cost, high repeatability and reliability by simplifying the manufacturing process step.

Abstract: Disclosed is a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof without using a trench isolation process and a sophisticated selective epitaxial growth (SEG) processes. According to this invention, the sophisticated isolation and the SEG techniques are derived by using simple and popular processes. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.

Abstract: The present invention provides a collector device in a bipolar device, having a lateral collector structure on a buried oxide layer. This collector has a high breakdown voltage for high power and operating at a high speed, by isolating a horizontal collector from a substrate by a buried oxide film and horizontally connecting a buried collector to a collector. The buried collector film is formed on the buried insulating film, surrounding the collector film and being horizontally connected to the collector film.

Abstract: The present invention relates to a metal silicon field effect transistor (MOSFET), and more particularly to a MOSFET, using a Si or SiGe channel to effectively adjust threshold voltage. The transistor according to the present invention can solve the problems, such as the punch-through caused by the short distance between the source region and the drain region, the decrease of the breakdown voltage between the source region and the drain region and the leakage current flowing into the bulk region beneath the channel due to the drain-induced barrier lowering. Furthermore, because the source region and the drain region are isolated from the semiconductor substrate by the lower insulation layer, the removal of the parasite junction capacitor speed up the transistor.

Abstract: The present invention relates to a metal silicon field effect transistor (MOSFET), and more particularly to a MOSFET, using a Si or SiGe channel to effectively adjust threshold voltage. The transistor according to the present invention can solve the problems, such as the punch-through caused by the short distance between the source region and the drain region, the decrease of the breakdown voltage between the source region and the drain region and the leakage current flowing into the bulk region beneath the channel due to the drain-induced barrier lowering. Furthermore, because the source region and the drain region are isolated from the semiconductor substrate by the lower insulation layer, the removal of the parasite junction capacitor speed up the transistor.

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth process without using a trench for isolating between elements. According to the invention, isolation between elements is derived by using a mask defining an emitter region and a second spacer. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth for a base is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.

Abstract: There is disclosed a method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor having a good conformity and an improved speed characteristic, which includes the steps of sequentially laminating an underlying nitride film, an oxide film, a polycrystalline silicon film and an upper nitride on a semiconductor substrate on which devices are separated and a collector is formed; sequentially etching said upper nitride film and said polycrystalline silicon film using the emitter as a mask, and then forming a side wall nitride film; selectively wet-etching said oxide film to form a side base linker opening; burying said base linker opening with a polycrystalline silicon; oxidizing said polycrystalline silicon film buried into said base linker opening and then removing said oxide film by means of the selective wet-etch process; removing said upper nitride and then forming a silicon/silicon germanium film as a base film on the exposed thereof; and forming an emitter said silicon/silicon germ

Abstract: Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxi

Abstract: An improved method for fabricating a heterojunction bipolar transistor which includes the steps of forming a buried collector, a collector thin film, and a collector sinker on a semiconductor substrate in order, forming a first silicon oxide film, a base electrode polysilicon layer, a nitride film, and an oxidation film on a resulting substrate exposing the first silicon oxidation film, forming a spacer insulation film at the lateral side of the exposed region, and defining an activation region, exposing the collector thin film of the activation region using a mask, and forming an auxiliary lateral film for an isolation of the device, forming a selective collector region by ion-implantating a dopant to the activation region which is limited by the auxiliary lateral film, removing the auxiliary lateral film, etching the exposed portion in an anisotropic etching method, and forming a shallow trench for a device isolation, forming a polysilicon lateral film to have a height which is the same as the height of the

Abstract: Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxi

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth and a polycide base electrode without using a trench for isolating between elements, thereby enhancing the performance thereof, which comprises the steps of: forming sequently a first oxidation film, an electrically conducting thin film and a second oxidation film on top of a substrate; patterning the second oxidation film and the conducting thin film to form a preliminary spacer; removing an exposed portion of the first oxidation film, and selectively growing a collector layer; oxidizing the collector layer to form a thermal oxidation film, and removing the preliminary spacer; depositing a polysilicon and forming a silicon oxidation film and a polysilicon spacer on the second oxidation film and the removed portion of the preliminary spacer, respectively; exposing the bas