Patents by Inventor Tae-Hyoung Koo

Tae-Hyoung Koo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9806036
    Abstract: A semiconductor wafer including a main body including first and second surfaces opposite each other, a notch including a recess on an outer periphery, a first bevel region formed along the outer periphery of the main body, including a first slope connecting the first and second surfaces and having a first height with respect to a straight line extending from a first point where the first surface and the first slope meet to a second point where the second surface and the first slope meet, and a second bevel region in contact with the recess or opening, including a second slope connecting the first and second surfaces and having a second height, different from the first height, with respect to a straight line extending from a third point where the first surface and the second slope meet to a fourth point where the second surface and the second slope meet.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-soo Kim, Sam-jong Choi, Sue-ryeon Kim, Tae-hyoung Koo, Hyun-hee Ju, Cheong-jun Kim, Ji-won You
  • Publication number: 20170200683
    Abstract: A semiconductor wafer including a main body including first and second surfaces opposite each other, a notch including a recess on an outer periphery, a first bevel region formed along the outer periphery of the main body, including a first slope connecting the first and second surfaces and having a first height with respect to a straight line extending from a first point where the first surface and the first slope meet to a second point where the second surface and the first slope meet, and a second bevel region in contact with the recess or opening, including a second slope connecting the first and second surfaces and having a second height, different from the first height, with respect to a straight line extending from a third point where the first surface and the second slope meet to a fourth point where the second surface and the second slope meet.
    Type: Application
    Filed: November 17, 2016
    Publication date: July 13, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: JONG-SOO KIM, Sam-jong Choi, Sue-ryeon Kim, Tae-hyoung Koo, Hyun-hee Ju, Cheong-jun Kim, Ji-won You
  • Patent number: 9589901
    Abstract: A wafer can be provided to include a single crystalline semiconductor material with a predetermined crystal orientation. The wafer can include a laser mark at a determined position on a front surface or on a back surface of the wafer, where the determined position is configured to indicate the predetermined crystal orientation of the single crystalline semiconductor material.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: March 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hyoung Koo, Samjong Choi, Dongjun Lee, Yongsun Ko
  • Publication number: 20150228588
    Abstract: A wafer can be provided to include a single crystalline semiconductor material with a predetermined crystal orientation. The wafer can include a laser mark at a determined position on a front surface or on a back surface of the wafer, where the determined position is configured to indicate the predetermined crystal orientation of the single crystalline semiconductor material.
    Type: Application
    Filed: October 21, 2014
    Publication date: August 13, 2015
    Inventors: Tae-Hyoung Koo, Samjong Choi, Dongjun Lee, Yongsun Ko
  • Publication number: 20140008705
    Abstract: A semiconductor device includes field regions formed in a substrate, and n-type impurity regions disposed between the field regions. At least one of the side surfaces of the field regions has a {100}, {310}, or {311} plane.
    Type: Application
    Filed: March 15, 2013
    Publication date: January 9, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon- Young Choi, Kyung-Ho Lee, Sang-Jun Choi, Tae-Hyoung Koo, Sam-Jong Choi
  • Patent number: 8497570
    Abstract: A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: July 30, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Ha Hwang, Young-Soo Park, Sam-Jong Choi, Joon-Young Choi, Tae-Hyoung Koo
  • Patent number: 8343853
    Abstract: A method of processing a semiconductor wafer includes preheating the wafer to a preheating temperature that is less than a peak temperature, heating the wafer from the preheating temperature to the peak temperature at a first ramp rate that averages about 100° C. per second or more, and, immediately after heating the wafer from the preheating temperature to the peak temperature, cooling the wafer at a second ramp rate that averages about ?70° C. per second or more from the peak temperature to the preheating temperature, wherein the peak temperature is about 1,100° C. or more.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hyoung Koo, Sam-jong Choi, Yeonsook Kim, Taesung Kim, Heesung Kim, KyooChul Cho, Joonyoung Choi
  • Publication number: 20120056304
    Abstract: A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface.
    Type: Application
    Filed: July 8, 2011
    Publication date: March 8, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-Ha Hwang, Young-Soo Park, Sam-Jong Choi, Joon-Young Choi, Tae-Hyoung Koo
  • Publication number: 20100148310
    Abstract: A method of processing a semiconductor wafer includes preheating the wafer to a preheating temperature that is less than a peak temperature, heating the wafer from the preheating temperature to the peak temperature at a first ramp rate that averages about 100° C. per second or more, and, immediately after heating the wafer from the preheating temperature to the peak temperature, cooling the wafer at a second ramp rate that averages about ?70° C. per second or more from the peak temperature to the preheating temperature, wherein the peak temperature is about 1,100° C. or more.
    Type: Application
    Filed: October 1, 2009
    Publication date: June 17, 2010
    Inventors: Tae-Hyoung Koo, Sam-jong Choi, Yeonsook Kim, Taesung Kim, Heesung Kim, KyooChul Cho, Joonyoung Choi