Patents by Inventor Tae-hyuk Ahn

Tae-hyuk Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8169012
    Abstract: A semiconductor device and a method of fabricating a semiconductor device provide high quality cylindrical capacitors. The semiconductor device includes a substrate defining a cell region and a peripheral circuit region, a plurality of capacitors in the cell region, and supports for supporting lower electrodes of the capacitors. The lower electrodes are disposed in a plurality of rows each extending in a first direction. A dielectric layer is disposed on the lower electrodes, and an upper electrode is disposed on the dielectric layer. The supports are in the form of stripes extending longitudinally in the first direction and spaced from each other along a second direction. Each of the supports engages the lower electrodes of a respective plurality of adjacent rows of the lower electrodes. Each one of the supports is also disposed at a different level in the device from the support that is adjacent thereto in the second direction.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: May 1, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-kug Bae, Si-hyeung Lee, Tae-hyuk Ahn, Seok-hwan Oh
  • Patent number: 8017485
    Abstract: Methods of fabricating a semiconductor device are provided, the methods include forming a first dielectric layer, a data storage layer, and a second dielectric layer, which are sequentially stacked, on a semiconductor substrate. A mask having a first opening exposing a first region of the second dielectric layer is formed on the second dielectric layer. A gate electrode filling at least a portion of the first opening is formed. A second opening exposing a second region of the second dielectric layer is formed by etching the mask such that the second region is spaced apart from the first region. A second dielectric pattern and a data storage pattern are formed by sequentially etching the exposed second region of the second dielectric layer and the data storage layer. The second dielectric pattern is formed to have a greater width than a lower surface of the gate electrode.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: September 13, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Du-Hyun Cho, Tae-Hyuk Ahn, Sang-Sup Jeong, Jin-Hyuk Yoo
  • Patent number: 7888725
    Abstract: An electronic device may include a substrate and a plurality of conductive electrodes on the substrate. Each of the conductive electrodes may have a respective electrode wall extending away from the substrate, and an electrode wall of at least one of the conductive electrodes may include a recessed portion. In addition, an insulating layer may be provided on the electrode wall, and portions of the electrode wall may be free of the insulating layer between the substrate and the insulating layer.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-joon Yeo, Tae-hyuk Ahn, Kwang-wook Lee, Jung-woo Seo, Jeong-sic Jeon
  • Patent number: 7851354
    Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: December 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-woo Seo, Jong-seo Hong, Tae-hyuk Ahn, Jeong-sic Jeon, Jun-sik Hong, Young-sun Cho
  • Publication number: 20100099248
    Abstract: Methods of fabricating a semiconductor device are provided, the methods include forming a first dielectric layer, a data storage layer, and a second dielectric layer, which are sequentially stacked, on a semiconductor substrate. A mask having a first opening exposing a first region of the second dielectric layer is formed on the second dielectric layer. A gate electrode filling at least a portion of the first opening is formed. A second opening exposing a second region of the second dielectric layer is formed by etching the mask such that the second region is spaced apart from the first region. A second dielectric pattern and a data storage pattern are formed by sequentially etching the exposed second region of the second dielectric layer and the data storage layer. The second dielectric pattern is formed to have a greater width than a lower surface of the gate electrode.
    Type: Application
    Filed: October 20, 2009
    Publication date: April 22, 2010
    Inventors: Du-Hyun Cho, Tae-Hyuk Ahn, Sang-Sup Jeong, Jin-Hyuk Yoo
  • Patent number: 7682778
    Abstract: Provided are contact photomasks and methods using such photomasks for fabricating semiconductor devices and forming contact plugs on portions of active regions exposed between gate lines. The elongated active regions are arrayed in a series of parallel groups with each group being, in turn, aligned along their longitudinal axes to form an acute angle with the gate lines. The contact photomask includes a plurality of openings arranged in parallel lines that are aligned at an angle offset from previously formed gate lines and which may be parallel to the active regions or may be aligned at an angle offset from the axes of both the groups of active regions and the gate lines. Processes for forming contact plugs using such photomasks may provide increased processing margin and extend the utility of conventional exposure equipment for semiconductor devices exhibiting increased integration density and/or built to more demanding design rules.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: March 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Woo Seo, Tae-Hyuk Ahn, Jong-Seo Hong
  • Publication number: 20090206399
    Abstract: A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.
    Type: Application
    Filed: April 27, 2009
    Publication date: August 20, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Chul PARK, Yong-Sun KO, Tae-Hyuk AHN
  • Patent number: 7534726
    Abstract: A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: May 19, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Chul Park, Yong-Sun Ko, Tae-Hyuk Ahn
  • Patent number: 7531414
    Abstract: A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: May 12, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Chul Park, Jun Seo, Tae-Hyuk Ahn, Hyuk-Jin Kwon, Jong-Heui Song, Dae-Keun Kang
  • Publication number: 20090102017
    Abstract: A semiconductor device and a method of fabricating a semiconductor device provide high quality cylindrical capacitors. The semiconductor device includes a substrate defining a cell region and a peripheral circuit region, a plurality of capacitors in the cell region, and supports for supporting lower electrodes of the capacitors. The lower electrodes are disposed in a plurality of rows each extending in a first direction. A dielectric layer is disposed on the lower electrodes, and an upper electrode is disposed on the dielectric layer. The supports are in the form of stripes extending longitudinally in the first direction and spaced from each other along a second direction. Each of the supports engages the lower electrodes of a respective plurality of adjacent rows of the lower electrodes. Each one of the supports is also disposed at a different level in the device from the support that is adjacent thereto in the second direction.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 23, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-kug BAE, Si-hyeung LEE, Tae-hyuk AHN, Seok-hwan OH
  • Patent number: 7511328
    Abstract: A semiconductor device and method of manufacturing the same having pad extending parts, the semiconductor device includes an isolation layer that defines an active region and a gate electrode which traverses the active region. A source region is provided in the active region at one side of the gate electrode, and a drain region is provided in the active region at a second side of the gate electrode. A first interlayer insulating layer covers the semiconductor substrate. A source landing pad is electrically connected to the source region, and a drain landing pad is electrically connected to the drain region. A pad extending part is laminated on one or more of the source landing pad and the drain landing pad. The pad extending part has an upper surface located in a plane above a plane corresponding to the upper surfaces of the source landing pad and the drain landing pad.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: March 31, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Woo Seo, Tae-Hyuk Ahn, Jong-Seo Hong
  • Publication number: 20090068809
    Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.
    Type: Application
    Filed: November 10, 2008
    Publication date: March 12, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-woo SEO, Jong-seo HONG, Tae-hyuk AHN, Jeong-sic JEON, Jun-sik HONG, Young-sun CHO
  • Patent number: 7491344
    Abstract: Disclosed herein is a method for etching a face of an object and more particularly a method for etching a rear face of a silicon substrate. The object having a silicon face is positioned so as to be spaced apart from a plasma-generating member by a predetermined interval distance. The plasma-generating member generates arc plasmas to form a plasma region. A reaction gas is allowed to pass through the plasma region to generate radicals having high energies and high densities. The radicals react with the object to etch the face of the object. The face of the object can be rapidly and uniformly etched.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: February 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung-Sik Park, Chang-Jin Kang, Tae-Hyuk Ahn, Kyeong-Koo Chi, Sang-Hun Seo
  • Patent number: 7491601
    Abstract: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer, and portions of the electrode most distant from the substrate may be free of the insulating spacer. Related methods and structures are also discussed.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: February 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-joon Yeo, Tae-hyuk Ahn, Kwang-wook Lee, Jung-woo Seo, Jeong-sic Jeon
  • Publication number: 20090032905
    Abstract: An electronic device may include a substrate and a plurality of conductive electrodes on the substrate. Each of the conductive electrodes may have a respective electrode wall extending away from the substrate, and an electrode wall of at least one of the conductive electrodes may include a recessed portion. In addition, an insulating layer may be provided on the electrode wall, and portions of the electrode wall may be free of the insulating layer between the substrate and the insulating layer.
    Type: Application
    Filed: October 3, 2008
    Publication date: February 5, 2009
    Inventors: In-joon Yeo, Tae-hyuk Ahn, Kwang-wook Lee, Jung-woo Seo, Jeong-sic Jeon
  • Publication number: 20090014833
    Abstract: An exemplary semiconductor device includes a semiconductor substrate on which lower electrodes are formed. The lower electrodes are arranged in an array including a rows extending substantially parallel to one another along a first direction. A stripe-shaped capacitor support pad is interposed between a pair of adjacent ones of the rows and is connected to lower electrodes in the pair of adjacent ones of the rows. The semiconductor device may include plurality of capacitors each including a one of the lower electrodes, a dielectric film, and an upper electrode. An upper end of the capacitor support pad is below the upper ends of the lower electrodes. A portion of the stripe-shaped capacitor support pad is interposed between adjacent ones of lower electrodes included within at least one of the rows and is connected to the adjacent ones of lower electrodes included within the at least one of the rows.
    Type: Application
    Filed: July 10, 2008
    Publication date: January 15, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kuk-Han YOON, Jong-Kyu KIM, Sang-Sup JEONG, Sung-Gil CHOI, Tae-Hyuk AHN
  • Patent number: 7462899
    Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: December 9, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-woo Seo, Jong-seo Hong, Tae-hyuk Ahn, Jeong-sic Jeon, Jun-sik Hong, Young-sun Cho
  • Publication number: 20080096347
    Abstract: An electronic device may include a substrate, a conductive layer on the substrate, and an insulating spacer. The conductive electrode may have an electrode wall extending away from the substrate. The insulating spacer may be provided on the electrode wall with portions of the electrode wall being free of the insulating spacer between the substrate and the insulating spacer, and portions of the electrode most distant from the substrate may be free of the insulating spacer. Related methods and structures are also discussed.
    Type: Application
    Filed: December 14, 2007
    Publication date: April 24, 2008
    Inventors: In-joon Yeo, Tae-hyuk Ahn, Kwang-wook Lee, Jung-woo Seo, Jeong-sic Jeon
  • Publication number: 20080090356
    Abstract: A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.
    Type: Application
    Filed: December 13, 2007
    Publication date: April 17, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Chul PARK, Jun SEO, Tae-Hyuk AHN, Hyuk-Jin KWON, Jong-Heui SONG, Dae-Keun KANG
  • Publication number: 20080064206
    Abstract: Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.
    Type: Application
    Filed: November 5, 2007
    Publication date: March 13, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-woo SEO, Tae-hyuk AHN, Jeong-sic JEON