Patents by Inventor Tae-hyun Han

Tae-hyun Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230251576
    Abstract: A semiconductor fabrication apparatus comprising a light source configured to emit light, a substrate stage arranged to receive a substrate exposed to the emitted light, a reticle arranged between the substrate stage and the light source, and a reticle stage arranged to receive the reticle. The reticle stage including a lower plate, an upper plate arranged above the lower plate, an actuator connected to the lower plate configured to move in a direction parallel to the upper plate, a first cable slab arranged between the upper plate and the lower plate and connected to one side of the actuator, and a first cable cover that surrounds an outer periphery of the first cable slab and contacts the lower plate when the first cable slab becomes bent.
    Type: Application
    Filed: September 26, 2022
    Publication date: August 10, 2023
    Inventors: OHKUG KWON, SANGHUN KIM, JUNGHWAN KIM, SANGBEOM PARK, YOUNGDUK SUH, JINWOOK JUNG, KUKBIN CHOI, DONGKYENG HAN, TAE-HYUN HAN
  • Publication number: 20140317401
    Abstract: A mobile certificate issue server, system, and method are provided. The mobile certificate issue server includes a certificate generation part for generating a certificate using a public key included in certificate issue request information received from a user terminal, an e-mail sending part for sending the certificate to an e-mail address accessible to the mobile terminal of a user, and a server-side certificate conversion part for converting the certificate into information having a recognition format capable of being recognized by the mobile terminal Here, the e-mail sending part sends the certificate through e-mail in an attachment form. The e-mail sending part stores the information having the recognition format in a file form, inserts the file into the e-mail as an attachment file, and sends the e-mail to the e-mail address accessible to the mobile terminal of the user.
    Type: Application
    Filed: April 26, 2013
    Publication date: October 23, 2014
    Applicant: UNETsystem, INC.
    Inventors: Sang Jun LEE, Bum Chul KWON, Tae Hyun HAN
  • Patent number: 7208365
    Abstract: Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: April 24, 2007
    Assignees: Samsung Electronics Co., Ltd., Kwang-youl Seo
    Inventors: Hee-soon Chae, Chung-woo Kim, Kwang-youl Seo, Tae-hyun Han, Byung-chul Kim, Joo-yeon Kim
  • Publication number: 20060273377
    Abstract: Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.
    Type: Application
    Filed: August 16, 2006
    Publication date: December 7, 2006
    Applicants: SAMSUNG ELECTRONICS CO., LTD., KWANG-YOUL SEO
    Inventors: Hee-soon Chae, Chung-woo Kim, Kwang-youl Seo, Tae-hyun Han, Byung-chul Kim, Joo-yeon Kim
  • Patent number: 7112842
    Abstract: Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: September 26, 2006
    Assignees: Samsung Electronics Co., Ltd., Kwang-Youl Seo
    Inventors: Hee-soon Chae, Chung-woo Kim, Kwang-youl Seo, Tae-hyun Han, Byung-chul Kim, Joo-yeon Kim
  • Publication number: 20050162958
    Abstract: Provided are a nonvolatile memory device and a method of manufacturing the same. The device includes a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and a channel region interposed between the source and drain regions; a first tunnel oxide layer disposed on the channel region near the source region; a second tunnel oxide layer disposed on the channel region near the drain region; a first charge trapping layer disposed on the first tunnel oxide layer; a second charge trapping layer disposed on the second tunnel oxide layer; a blocking oxide layer covering the first and second charge trapping layers; a charge isolation layer interposed between the first and second charge trapping layers; and a gate electrode disposed on the blocking oxide layer.
    Type: Application
    Filed: October 29, 2004
    Publication date: July 28, 2005
    Applicants: Samsung Electronics Co., Ltd., Kwang-youl Seo
    Inventors: Hee-soon Chae, Chung-woo Kim, Kwang-youl Seo, Tae-hyun Han, Byung-chul Kim, Joo-yeon Kim