Abstract: An oxide or nitride semiconductor layer is formed over a substrate. A first conductive layer including a first element and a second element, and a second conductive layer including the second element are formed over the semiconductor layer. The first element is oxidized or nitrogenized near an interface region between the first conductive layer and the oxide or nitride semiconductor layer by heat treatment or laser irradiation. The Gibbs free energy of oxide formation of the first element is lower than those of the second element or any element in the oxide or nitride semiconductor layer.

Abstract: An oxide or nitride semiconductor layer is formed over a substrate. A first conductive layer including a first element and a second element, and a second conductive layer including the second element are formed over the semiconductor layer. The first element is oxidized or nitrogenized near an interface region between the first conductive layer and the oxide or nitride semiconductor layer by heat treatment or laser irradiation. The Gibbs free energy of oxide formation of the first element is lower than those of the second element or any element in the oxide or nitride semiconductor layer.

Abstract: An oxide or nitride semiconductor layer is formed over a substrate. A first conductive layer including a first element and a second element, and a second conductive layer including the second element are formed over the semiconductor layer. The first element is oxidized or nitrogenized near an interface region between the first conductive layer and the oxide or nitride semiconductor layer by heat treatment or laser irradiation. The Gibbs free energy of oxide formation of the first element is lower than those of the second element or any element in the oxide or nitride semiconductor layer.

Abstract: An oxide or nitride semiconductor layer is formed over a substrate. A first conductive layer including a first element and a second element, and a second conductive layer including the second element are formed over the semiconductor layer. The first element is oxidized or nitrogenized near an interface region between the first conductive layer and the oxide or nitride semiconductor layer by heat treatment or laser irradiation. The Gibbs free energy of oxide formation of the first element is lower than those of the second element or any element in the oxide or nitride semiconductor layer.

Abstract: Provided is a method of fabricating a semiconductive oxide thin-film transistor (TFT) substrate. The method includes forming gate wiring on an insulation substrate; and forming a structure in which a semiconductive oxide film pattern and data wiring are stacked on the gate wiring, wherein the semiconductive oxide film pattern is selectively patterned to have channel regions of first thickness and source/drain regions of greater second thickness and where image data is coupled to the source regions by data wiring formed on the source regions. According to a 4-mask embodiment, the data wiring and semiconductive oxide film pattern are defined by a shared etch mask.

Abstract: Provided is a method of fabricating a semiconductive oxide thin-film transistor (TFT) substrate. The method includes forming gate wiring on an insulation substrate; and forming a structure in which a semiconductive oxide film pattern and data wiring are stacked on the gate wiring, wherein the semiconductive oxide film pattern is selectively patterned to have channel regions of first thickness and source/drain regions of greater second thickness and where image data is coupled to the source regions by data wiring formed on the source regions. According to a 4-mask embodiment, the data wiring and semiconductive oxide film pattern are defined by a shared etch mask.

Abstract: Provided is a method of fabricating a semiconductive oxide thin-film transistor (TFT) substrate. The method includes forming gate wiring on an insulation substrate; and forming a structure in which a semiconductive oxide film pattern and data wiring are stacked on the gate wiring, wherein the semiconductive oxide film pattern is selectively patterned to have channel regions of first thickness and source/drain regions of greater second thickness and where image data is coupled to the source regions by data wiring formed on the source regions. According to a 4-mask embodiment, the data wiring and semiconductive oxide film pattern are defined by a shared etch mask.

Abstract: A thin film transistor (TFT) array substrate is provided. The thin film transistor (TFT) array substrate includes an insulating substrate, an oxide semiconductor layer formed on the insulating substrate and including an additive element, a gate electrode overlapping the oxide semiconductor layer, and a gate insulating layer interposed between the oxide semiconductor layer and the gate electrode, wherein the oxygen bond energy of the additive element is greater than that of a base element of the oxide semiconductor layer.

Abstract: A display substrate includes; a base substrate, a deformation preventing layer disposed on a lower surface of the base substrate, wherein the deformation preventing layer applies a force to the base substrate to prevent the base substrate from bending, a gate line disposed on an upper surface of the base substrate, a data line disposed on the base substrate, and a pixel electrode disposed on the base substrate.

Abstract: An oxide or nitride semiconductor layer is formed over a substrate. A first conductive layer including a first element and a second element, and a second conductive layer including the second element are formed over the semiconductor layer. The first element is oxidized or nitrogenized near an interface region between the first conductive layer and the oxide or nitride semiconductor layer by heat treatment or laser irradiation. The Gibbs free energy of oxide formation of the first element is lower than those of the second element or any element in the oxide or nitride semiconductor layer.

Abstract: Provided is a method of fabricating a semiconductive oxide thin-film transistor (TFT) substrate. The method includes forming gate wiring on an insulation substrate; and forming a structure in which a semiconductive oxide film pattern and data wiring are stacked on the gate wiring, wherein the semiconductive oxide film pattern is selectively patterned to have channel regions of first thickness and source/drain regions of greater second thickness and where image data is coupled to the source regions by data wiring formed on the source regions. According to a 4-mask embodiment, the data wiring and semiconductive oxide film pattern are defined by a shared etch mask.

Abstract: An LCD includes a substrate; a first transistor formed on the substrate, the first transistor having a MILC (metal-induced lateral crystallization) region formed on a substrate with a semiconductor material and including a channel region; and MIC (metal-induced crystallization) regions formed on sides of the MILC region with a semiconductor material, wherein at least one boundary between the MILC region and one of the MIC regions is located outside the channel region; a second transistor formed on the substrate, the second transistor having a MILC (metal-induced lateral crystallization) region formed on the same substrate with a semiconductor material and including a channel region; and MIC (metal-induced crystallization) regions formed on sides of the MILC region with a semiconductor material, wherein at least one boundary between the MILC region and one of the MIC regions is located outside the channel region; and a third transistor formed on the substrate, the third transistor having an amorphous silicon l

Abstract: An LCD includes a substrate; a first transistor formed on the substrate, the first transistor having a MILC (metal-induced lateral crystallization) region formed on a substrate with a semiconductor material and including a channel region; and MIC (metal-induced crystallization) regions formed on sides of the MILC region with a semiconductor material, wherein at least one boundary between the MILC region and one of the MIC regions is located outside the channel region; a second transistor formed on the substrate, the second transistor having a MILC (metal-induced lateral crystallization) region formed on the same substrate with a semiconductor material and including a channel region; and MIC (metal-induced crystallization) regions formed on sides of the MILC region with a semiconductor material, wherein at least one boundary between the MILC region and one of the MIC regions is located outside the channel region; and a third transistor formed on the substrate, the third transistor having an amorphous silicon l

Abstract: A method of manufacturing a TFT which can improve realibility by planarizing the surface of a polysilicon layer as a channel layer, is disclosed. According to the present invention, an amorphous silicon layer is formed on an insulating layer substrate and crystallized by excimer layer annealing process, to form a polysilicon layer. Next, the surface of the polysilicon layer is oxidized to form an oxide layer. At this time the sufrace of the polsyilicon under the oxide layer become smooth. Preferably, the oxide layer is formed by oxiation process using ECR (Electron Cyclon Resonator) plasma or using one selected from the group consisting of O2, O2N2, O2N2O, O2NH3 and NO. Thereafter, the oxide layer is removed to expose the polysilicon layer and then a gate insulating layer is formed on the exposed polysilicon layer. Preferably, the gate insulating layer is formed to one selected from the group consisting of a SiO2 layer, a SiN layer, a SiON layer and a TEOS oxide layer.

Abstract: A transistor includes an MILC (metal-induced lateral crystallization) region formed on a substrate with a semiconductor material and including a channel region, and a plurality of MIC (metal-induced crystallization) regions formed on the sides of the MILC region with a semiconductor material, wherein at least one boundary between the MILC region and one of the MIC regions is located outside the channel region. A method of fabricating a transistor includes the steps of forming an MILC (metal-induced lateral crystallization) region on a substrate using a semiconductor material, the MILC region including a channel region, and forming a plurality of MIC (metal-induced crystallization) regions formed on sides of the MILC region using a semiconductor material, wherein at least one boundary between the MILC region and one of the MIC regions is located outside the channel region.