Abstract: A circuit for measuring clock jitter includes: an internal signal generator configured to generate an internal clock signal and a single pulse signal, respectively synchronized with an input clock signal; a plurality of delay units being connected in series with each other and configured to generate respective delayed clock signals; a plurality of latch circuits configured to latch the single pulse signal in synchronization with the respective delayed clock signals, and output sampling signals; and a count sub-circuit configured to output a count value resulting from counting a number of active sampling signals of the sampling signals.

Abstract: Provided are a semiconductor device including a modulator for PSK communication and a semiconductor device including a demodulator for PSK communication, and a PSK communication system. The semiconductor device includes a reference clock generator to generate a reference clock signal, a phase locked loop (PLL) to receive the reference clock signal and generate a first clock signal, an integer divider circuit to generate a second clock signal by delaying a rising edge of the reference clock signal by a product of a predetermined integer value included in transmission data and a phase interval, and a processing unit to generate a first transmission signal. The first transmission signal is phase-shifted from a first rising edge of the second clock signal. The phase interval is dependent on a ratio of the frequency of the first clock signal to the frequency of the reference clock signal.

Abstract: A touch screen panel includes a transparent substrate, a first sensing line and a second sensing line. The first sensing line includes first sensing cells arranged along a first direction and first connection patterns coupling the first sensing cells. The second sensing line includes second sensing cells arranged in a second direction substantially perpendicular to the first direction, and second connection patterns coupling the second sensing cells. At least one of the first and the second sensing cells includes openings and conductive patterns located in the openings.

Abstract: A display device includes: a lower substrate; a display layer disposed on the lower substrate and including an electro-optical active layer; a touch electrode layer disposed on the display layer and including first touch electrodes arranged in columns and second touch electrodes arranged in rows intersecting the columns; connections connecting adjacent first electrodes in each of the columns, connections each including islands disposed on the second electrodes, and bridges connecting the first electrodes to the islands; and an insulating layer electrically separating the second touch electrodes and the bridges. The bridges each include a first end that is directly connected to one of the first electrodes and a second end that is indirectly connected to another one of the first electrodes.

Abstract: A current reference circuit includes a reference current supply unit configured to generate a reference current having a target current level, a current-frequency converter configured to receive a first temporary reference current corresponding to the reference current from the reference current supply unit and to generate a first comparison clock signal in response to the first temporary reference current, and a first current compensation unit configured to generate a first current compensation signal used for the first temporary reference current to reach the target current level in response to a frequency of a reference clock signal and a frequency of the first comparison clock signal.

Abstract: A touch screen panel may include a first sensing electrode that has a recess. The touch screen panel may further include a second sensing electrode that immediately neighbors the first sensing electrode. The touch screen panel may further include a dummy member that is disposed in the recess and is electrically insulated from the first sensing electrode. The touch screen panel may further include a static electricity induction member that is electrically connected to the second sensing electrode. A portion of the static electricity induction member may overlap the dummy member and may be electrically insulated from the dummy member.

Abstract: Provided are a semiconductor device including a modulator for PSK communication and a semiconductor device including a demodulator for PSK communication, and a PSK communication system. The semiconductor device includes a reference clock generator to generate a reference clock signal, a phase locked loop (PLL) to receive the reference clock signal and generate a first clock signal, an integer divider circuit to generate a second clock signal by delaying a rising edge of the reference clock signal by a product of a predetermined integer value included in transmission data and a phase interval, and a processing unit to generate a first transmission signal. The first transmission signal is phase-shifted from a first rising edge of the second clock signal. The phase interval is dependent on a ratio of the frequency of the first clock signal to the frequency of the reference clock signal.

Abstract: A touch screen panel includes a transparent substrate, a first sensing line and a second sensing line. The first sensing line includes first sensing cells arranged along a first direction and first connection patterns coupling the first sensing cells. The second sensing line includes second sensing cells arranged in a second direction substantially perpendicular to the first direction, and second connection patterns coupling the second sensing cells. At least one of the first and the second sensing cells includes openings and conductive patterns located in the openings.

Abstract: Provided are a digital phase-locked loop (DPLL) having improved signal characteristics, and a method of operating the DPLL. The DPLL includes a first tracking unit configured to receive a reference signal and a feedback signal that is generated by feeding back an output signal of the DPLL, track the feedback signal, and output a delayed reference signal, and a second tracking unit configured to receive a delayed feedback signal generated by delaying the feedback signal, and the delayed reference signal, and generate an output signal of the DPLL, of which a frequency is controlled according to a phase difference between the delayed feedback signal and the delayed reference signal.

Abstract: Provided are a semiconductor device and a phase-locked loop (PLL) including the same. The semiconductor device including an output node from which an output signal is output, a first transistor which has a drain connected to the output node and is gated by a first signal to increase a voltage level of the output node, a second transistor which has a drain connected to the output node, is gated by a second signal which is a complementary signal of the first signal, and reduces the voltage level of the output node, a pull-up circuit which provides a first compensation current varying according to the voltage level of the output node to a source of the first transistor, and a pull-down circuit which provides a second compensation current varying according to the voltage level of the output node to a source of the second transistor.

Abstract: A frequency doubler includes a voltage controlled oscillator outputting N (where, N is a natural number) signals having a first period and having different phases, and an XOR circuit receiving the N signals and outputting a signal having a second period that corresponds to a half of the first period, wherein the voltage controlled oscillator includes N nodes that correspond to the N signals and inverter units respectively connecting the N nodes, the N nodes are arranged so that, if a signal that starts from any one start node of the N nodes passes through the same number of the inverter units, it recurs to the corresponding start node, the XOR gate includes a first unit block set including N unit blocks that are connected to the same output node and match the N nodes in a one-to-one manner, and a second unit block set that is substantially the same as the first unit block set, wherein the first and second unit block sets share the output node.

Abstract: Provided are a digital phase-locked loop (DPLL) having improved signal characteristics, and a method of operating the DPLL. The DPLL includes a first tracking unit configured to receive a reference signal and a feedback signal that is generated by feeding back an output signal of the DPLL, track the feedback signal, and output a delayed reference signal, and a second tracking unit configured to receive a delayed feedback signal generated by delaying the feedback signal, and the delayed reference signal, and generate an output signal of the DPLL, of which a frequency is controlled according to a phase difference between the delayed feedback signal and the delayed reference signal.

Abstract: Provided are a semiconductor device and a phase-locked loop (PLL) including the same. The semiconductor device including an output node from which an output signal is output, a first transistor which has a drain connected to the output node and is gated by a first signal to increase a voltage level of the output node, a second transistor which has a drain connected to the output node, is gated by a second signal which is a complementary signal of the first signal, and reduces the voltage level of the output node, a pull-up circuit which provides a first compensation current varying according to the voltage level of the output node to a source of the first transistor, and a pull-down circuit which provides a second compensation current varying according to the voltage level of the output node to a source of the second transistor.

Abstract: A frequency doubler includes a voltage controlled oscillator outputting N (where, N is a natural number) signals having a first period and having different phases, and an XOR circuit receiving the N signals and outputting a signal having a second period that corresponds to a half of the first period, wherein the voltage controlled oscillator includes N nodes that correspond to the N signals and inverter units respectively connecting the N nodes, the N nodes are arranged so that, if a signal that starts from any one start node of the N nodes passes through the same number of the inverter units, it recurs to the corresponding start node, the XOR gate includes a first unit block set including N unit blocks that are connected to the same output node and match the N nodes in a one-to-one manner, and a second unit block set that is substantially the same as the first unit block set, wherein the first and second unit block sets share the output node.

Abstract: A pixel clock generator is provided. The pixel clock generator includes a phase-locked-loop (PLL) circuit that generates, from an oscillation signal having a first frequency of tens of MHz, a multi-phase oscillation signal having a second frequency of several GHz; and a frequency/phase adjusting circuit that synchronizes the multi-phase oscillation signal with a horizontal sync signal to generate a first oscillation signal, frequency-divides the first oscillation signal to generate a second oscillation signal, and adjusts a phase of the second oscillation signal to generate the pixel clock.

Abstract: A display device includes: a lower substrate; a display layer disposed on the lower substrate and including an electro-optical active layer; a touch electrode layer disposed on the display layer and including first touch electrodes arranged in columns and second touch electrodes arranged in rows intersecting the columns; connections connecting adjacent first electrodes in each of the columns, connections each including islands disposed on the second electrodes, and bridges connecting the first electrodes to the islands; and an insulating layer electrically separating the second touch electrodes and the bridges. The bridges each include a first end that is directly connected to one of the first electrodes and a second end that is indirectly connected to another one of the first electrodes.

Abstract: A touch screen panel may include a first sensing electrode that has a recess. The touch screen panel may further include a second sensing electrode that immediately neighbors the first sensing electrode. The touch screen panel may further include a dummy member that is disposed in the recess and is electrically insulated from the first sensing electrode. The touch screen panel may further include a static electricity induction member that is electrically connected to the second sensing electrode. A portion of the static electricity induction member may overlap the dummy member and may be electrically insulated from the dummy member.

Abstract: A pixel clock generator is provided. The pixel clock generator includes a phase-locked-loop (PLL) circuit that generates, from an oscillation signal having a first frequency of tens of MHz, a multi-phase oscillation signal having a second frequency of several GHz; and a frequency/phase adjusting circuit that synchronizes the multi-phase oscillation signal with a horizontal sync signal to generate a first oscillation signal, frequency-divides the first oscillation signal to generate a second oscillation signal, and adjusts a phase of the second oscillation signal to generate the pixel clock.

Abstract: A method of operating a pixel clock generator (PCG), the method including generating N clock signals according to a control voltage signal, the N clock signals having different phases and N being a natural number; generating M frequency-divided clock signals based on the N clock signals, the M frequency-divided clock signals having different phases and M being a natural number greater than N; and generating a pixel clock signal based on at least two selected ones of the M frequency-divided clock signals.

Abstract: A touch screen panel includes a transparent substrate, a first sensing line and a second sensing line. The first sensing line includes first sensing cells arranged along a first direction and first connection patterns coupling the first sensing cells. The second sensing line includes second sensing cells arranged in a second direction substantially perpendicular to the first direction, and second connection patterns coupling the second sensing cells. At least one of the first and the second sensing cells includes openings and conductive patterns located in the openings.