Abstract: A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programmable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.

Abstract: Disclosed herein are image-based object recognition method and system by and in which a learning server performs image-based object recognition based on the learning of environment variable data. The image-based object recognition method includes: receiving an image acquired through at least one camera, and segmenting the image on a per-frame basis; primarily learning labeling results for one or more objects in the image segmented on a per-frame basis; performing primary reasoning by performing object detection in the image through a model obtained as a result of the primary learning; performing data labeling based on the results of the primary reasoning, and performing secondary learning with weights allocated to respective boxes obtained by the primary reasoning and estimated as object regions; and finally detecting one or more objects in the image through a model generated as a result of the secondary learning.

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.

Abstract: Provided are a Peripheral Component Interconnect Express (PCIe) interface device and a method of operating the same. The PCIe interface device includes a first buffer, a second buffer, and a buffer controller. The first buffer may be configured to store a plurality of first transaction layer packets received from multiple functions. The second buffer may be configured to store a plurality of second transaction layer packets received from the multiple functions. The buffer controller may be configured to, when a first buffer of a switch is full, realign an order in which the plurality of second transaction layer packets are to be output from the second buffer to the switch, based on IDs of the plurality of second transaction layer packets.

Abstract: Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.

Abstract: A method of operating a Peripheral Component Interconnect Express (PCIe) device including a first port and a second port comprises: performing a first link training operation to link up a first host with a first link of the first port; operating in a single port mode when the first link training operation is completed; performing a lane reduce operation to reduce a lane corresponding to the first link in response to a mode change request received from the first host; and performing a second link training operation to link up a second host with a second link of the second port when a status of the first link is an L0 state.

Abstract: Provided is a flexible organic electroluminescent device and a method for fabricating the same. In the flexible electroluminescent device, line hole patterns are formed on surfaces of a plurality of inorganic layers positioned in a pad region in which a flexible printed circuit board is connected to prevent a path of cracks caused by repeated bending and spreading of the organic electroluminescent device from spreading to the interior of the device.

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device includes a PCIe layer and a PCIe controller. The PCIe layer performs communication between a host and a Direct Memory Access (DMA) device. The PCIe controller switches an operating clock from a PCIe clock generated based on a reference clock to an internal clock, processes data of the PCIe layer on the basis of the internal clock, and recovers a link with respect to the host, when a reset signal received from the host is asserted or the reference clock is off.

Abstract: Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

Abstract: A PCIe device setting, when a fail lane is detected during a link setting operation, a link by using remaining lanes includes a plurality of lanes comprising a plurality of ports, and a link controller setting a link including the plurality of lanes, wherein the link is set to have a link width that includes remaining lanes, except for a fail lane from among the plurality of lanes, wherein the fail lane from among the plurality of lanes has a state in which the fail lane is unable to form a link with remaining lanes that have not failed from among the plurality of lanes.

Abstract: A peripheral component interconnect express (PCIe) interface system is provided to include a PCIe interface device, a host, and a non-volatile memory express (NVMe) device connected to the host through the interface device. The host includes a host memory configured to store information on a command to be executed on the NVMe device and a command that has been executed on the NVMe device, and an NVMe driver configured to transmit the command to be executed on the NVMe device to the host memory, and output a doorbell signal indicating that the command to be executed on the NVMe device has been stored in the host memory to the NVMe device. The NVMe device requests to the host memory to register a lightweight notification (LN) indicating a position in which the command to be executed on the NVMe device is stored.

Abstract: A storage system includes a master storage device for storing data based on a RAID level determined by a host, a slave storage device for storing the data according to a command distributed from the master storage device, and a controller hub for coupling the slave storage device to the master storage device, wherein the master storage device is further configured to transfer the command to the slave storage device through the controller hub when the master storage device receives a command processing request from the host, transmit a complete queue (CQ) to the host when operations of the master storage device and the slave storage device are completed in response to the command processing request, and request a host to allocate a capacity to each function in the master storage device and the at least one of the plurality of slave storage devices based on a reference capacity.

Abstract: A peripheral component interconnect express (PCIe) interface device is provided to include: a root complex configured to support a PCIe port, a memory connected to an input/output structure through the root complex, a switch connected to the root complex through a link and configured to transmit a transaction, and an end point connected to the switch through the link to transmit and receive a packet. The PCIe interface device may perform a link power management by changing a state of the link in response to a detection of an idle state of the link.

Abstract: A device is provided to include: a transceiver configured to transmit and receive data; and a skip ordered set (SKP OS) control logic in communication with the transceiver and configured to generate an SKP OS and control the transceiver to transmit the SKP OS and a data block to a link connecting to an external device and including a plurality of lanes. The SKP OS control logic is configured to increase or decrease transmission interval of the SKP OS based on a transmission history of the SKP OS, in response to an entry of the link to a recovery state that is used to recover the link from an error.

Abstract: A Peripheral Component Interconnect express (PCIe) device includes: a plurality of ports forming a plurality of lanes; and a link controller configured to set a link including the plurality of lanes to allocate non-sequential lane numbers to lanes adjacent to each other among the plurality of lanes.

Abstract: Provided herein may be an interface device and a method of operating the same. The interface device may include a first port configured to enable communication with a host, a second port configured to enable communication with the host, and a function manager including a plurality of variable functions that are selectively assignable to at least one of the first port and the second port.

Abstract: A storage system includes a master storage device for storing data based on a RAID level determined by a host, a slave storage device for storing the data according to a command distributed from the master storage device, and a controller hub for coupling the slave storage device to the master storage device, wherein the master storage device is further configured to transfer the command to the slave storage device through the controller hub when the master storage device receives a command processing request from the host, transmit a complete queue (CQ) to the host when operations of the master storage device and the slave storage device are completed in response to the command processing request, and request a host to allocate a capacity to each function in the master storage device and the at least one of the plurality of slave storage devices based on a reference capacity.

Abstract: A PCIe device and a method of operating the same are provided. The PCIe device may include a throughput calculator configured to calculate a throughput of each of a plurality of functions, a throughput analysis information generator configured to generate throughput analysis information indicating a result of a comparison between a throughput limit and the calculated throughput, a delay time information generator configured to generate a delay time for delaying a command fetch operation for each function based on the throughput analysis information, a command lookup table storage configured to store command-related information and a delay time of a function corresponding to a target command, the command-related information including information related to the target command to be fetched from a host, and a command fetcher configured to fetch the target command based on the command-related information and the delay time of the corresponding function.

Abstract: Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.