Abstract: Disclosed herein is a photodetector utilizing graphene. A single-layer graphene channel is formed on a semiconductor substrate doped with n-type impurity. The graphene channel has an end connected to a source electrode and is physically separated from a drain electrode. Light having passed through a gate insulation layer and a gate electrode generates electron-hole pairs at the interface between the graphene channel and the semiconductor substrate forming a Schottky junction, and a photocurrent is generated by a Schottky barrier. In addition, the Schottky barrier is changed according to an applied gate voltage, thereby changing the photocurrent.

Abstract: A portable system, method thereof, and a power consumption controller for controlling power consumption in a portable system are described. The portable system may include a storage unit, a module processing data, and a controller regulating power supplied to the module. The controller may regulate the module to perform a backup operation when a power saving mode begins and to interrupt the power after the backup operation is completed.

Abstract: A portable system, method thereof, and a power consumption controller for controlling power consumption in a portable system are described. The portable system may include a storage unit, a module processing data, and a controller regulating power supplied to the module. The controller may regulate the module to perform a backup operation when a power saving mode begins and to interrupt the power after the backup operation is completed.

Abstract: A semiconductor memory device having a fixed CAS latency during a normal operation and various CAS latencies during a test mode. The semiconductor memory device a master signal generator for generating a master signal in response to a power-up signal and a latency test signal. A plurality of fuse information units generate fuse information signals in response to the power-up signal and the master signal. A plurality of mode register set (MRS) address information units receive address bits during an interval where an address window signal is activated to generate MRS address latch signals in response to a MRS addressing signal. A CAS latency determining unit generates CAS latency select signals in response to the fuse information signals and the MRS address latch signals, wherein the CAS latency select signals provide a fixed CAS latency during a normal mode of operation of the semiconductor device and varying CAS latencies during a test mode of operation of the semiconductor device.

Abstract: A semiconductor memory device having a fixed CAS latency during a normal operation and various CAS latencies during a test mode. The semiconductor memory device a master signal generator for generating a master signal in response to a power-up signal and a latency test signal. A plurality of fuse information units generate fuse information signals in response to the power-up signal and the master signal. A plurality of mode register set (MRS) address information units receive address bits during an interval where an address window signal is activated to generate MRS address latch signals in response to a MRS addressing signal. A CAS latency determining unit generates CAS latency select signals in response to the fuse information signals and the MRS address latch signals, wherein the CAS latency select signals provide a fixed CAS latency during a normal mode of operation of the semiconductor device and varying CAS latencies during a test mode of operation of the semiconductor device.