Patents by Inventor Tae-Joong Song

Tae-Joong Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10811357
    Abstract: An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Boong Lee, Jung-Ho Do, Tae-Joong Song, Seung-Young Lee, Jong-Hoon Jung, Ji-Su Yu
  • Patent number: 10803226
    Abstract: An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ho Do, Jong-Hoon Jung, Seung-Young Lee, Tae-Joong Song
  • Patent number: 10803971
    Abstract: A device for supporting a test mode for memory testing according to an example embodiment of the inventive concepts may include a memory configured to receive and store writing data and output reading data from the stored writing data; an error correction code (ECC) engine configured to generate the writing data by encoding input data and to generate output data by correcting error bits of N bits or less included in receiving data when N is a positive integer; and an error insertion circuit configured to provide the reading data to the ECC engine as the receiving data in a normal mode and to provide data obtained by inverting at least one bit of less than N bits of the reading data to the ECC engine as the receiving data in the test mode.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-soo Pyo, Hyun-taek Jung, Tae-joong Song
  • Publication number: 20200294905
    Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 17, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-gyum KIM, Ha-young KIM, Tae-joong SONG, Jong-hoon JUNG, Gi-young YANG, Jin-young LIM
  • Patent number: 10762958
    Abstract: A method of controlling a reference cell in a resistive memory to identify values stored in a plurality of memory cells is provided. The method includes writing a first value to the plurality of memory cells, providing, to the reference cell, monotonically increasing or monotonically decreasing reference currents. The method includes reading the plurality of memory cells as each of the reference currents is provided to the reference cell, and determining a read reference current based on an aggregation of results of the reading.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-soo Pyo, Hyun-taek Jung, So-hee Hwang, Tae-joong Song
  • Publication number: 20200235126
    Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.
    Type: Application
    Filed: April 8, 2020
    Publication date: July 23, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-young KIM, Chang-beom Kim, Hyun-jeong Roh, Tae-joong Song, Dal-hee Lee, Sung-we Cho
  • Patent number: 10672702
    Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-gyum Kim, Ha-young Kim, Tae-joong Song, Jong-hoon Jung, Gi-young Yang, Jin-young Lim
  • Publication number: 20200159984
    Abstract: Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho DO, Jong-hoon JUNG, Ji-Su YU, Seung-young LEE, Tae-joong SONG, Jae-boong LEE
  • Patent number: 10651201
    Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-young Kim, Chang-beom Kim, Hyun-jeong Roh, Tae-joong Song, Dal-hee Lee, Sung-we Cho
  • Publication number: 20200135721
    Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.
    Type: Application
    Filed: January 2, 2020
    Publication date: April 30, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho DO, Sang-hoon BAEK, Tae-joong SONG, Jong-hoon JUNG, Seung-young LEE
  • Patent number: 10600466
    Abstract: A resistive memory device includes: a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output voltage; a word line power path connected to the switch circuit to receive the output voltage; and a word line driver driving a word line according to a voltage applied to the word line power path, wherein a write command starts to be received after a certain delay following the activation of the write enable signal, and a write operation is performed within an activation period of the write enable signal in response to the received write command.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suk-Soo Pyo, Hyun-Taek Jung, Tae-Joong Song
  • Patent number: 10579771
    Abstract: Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho Do, Jong-hoon Jung, Ji-su Yu, Seung-young Lee, Tae-joong Song, Jae-boong Lee
  • Patent number: 10573643
    Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: February 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho Do, Sang-hoon Baek, Tae-joong Song, Jong-hoon Jung, Seung-young Lee
  • Publication number: 20200034508
    Abstract: An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.
    Type: Application
    Filed: October 1, 2019
    Publication date: January 30, 2020
    Inventors: Jung-Ho Do, Jong-Hoon Jung, Seung-Young Lee, Tae-Joong Song
  • Patent number: 10445455
    Abstract: An integrated circuit includes: a lower layer including first and second lower patterns extending in a first direction; a first via arranged on the first lower pattern, and a second via arranged on the second lower pattern; a first upper pattern arranged on the first via; and a second upper pattern arranged on the second via, a first color is assigned to the first upper pattern, a second color is assigned to the second upper pattern, the first and second upper patterns are adjacent to each other in a second direction, and the first via is arranged in a first edge region of the first lower pattern, the first edge region being farther away from the second lower pattern than a second edge region of the first lower pattern, the second edge region being opposite to the first edge region.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ho Do, Jong-Hoon Jung, Seung-Young Lee, Tae-Joong Song
  • Publication number: 20190311755
    Abstract: A resistive memory device includes: a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output voltage; a word line power path connected to the switch circuit to receive the output voltage; and a word line driver driving a word line according to a voltage applied to the word line power path, wherein a write command starts to be received after a certain delay following the activation of the write enable signal, and a write operation is performed within an activation period of the write enable signal in response to the received write command.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 10, 2019
    Inventors: Suk-Soo Pyo, Hyun-Taek Jung, Tae-Joong Song
  • Patent number: 10433352
    Abstract: An operation method of a first communication node, which controls a plurality of communication nodes included in a mobile xhaul network supporting mobility, may comprise performing an attach procedure between the first communication node and a second communication node among the plurality of communication nodes; configuring a path for communications between the second communication node and a third communication node for which attach procedure has been completed among the plurality of communication nodes; and supporting communications of the second communication node and the third communication node using the configured path.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: October 1, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Seung Kwon Cho, Seok Ki Kim, Won Ik Kim, Eun Kyung Kim, Jae Heung Kim, Jae Su Song, Sung Pil Shin, Sei Yun Shin, Mi Young Yun, Soo Jung Jung, Yun Hee Cho, Tae Joong Kim, Seung Kwon Baek
  • Publication number: 20190287891
    Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.
    Type: Application
    Filed: June 6, 2019
    Publication date: September 19, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-gyum KIM, Ha-young KIM, Tae-joong SONG, Jong-hoon JUNG, Gi-young YANG, Jin-young LIM
  • Publication number: 20190252297
    Abstract: An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Inventors: JUNG-HO DO, TAE-JOONG SONG, SEUNG-YOUNG LEE, JONG-HOON JUNG
  • Patent number: 10373664
    Abstract: A resistive memory device includes: a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output voltage; a word line power path connected to the switch circuit to receive the output voltage; and a word line driver driving a word line according to a voltage applied to the word line power path, wherein a write command starts to be received after a certain delay following the activation of the write enable signal, and a write operation is performed within an activation period of the write enable signal in response to the received write command.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suk-Soo Pyo, Hyun-Taek Jung, Tae-Joong Song