Abstract: A semiconductor device may include a word line, a bit line crossing the word line, and a memory cell coupled to the word line and the bit line to receive an electrical signal to control the memory cell and including a switching material layer and an oxidation-reduction reversible material layer that is in contact with the switching material layer to allow for either oxidation reaction or reduction reaction to occur in response to different amplitudes and different polarities of the electrical signal, wherein the oxidation-reduction reversible material layer and the switching material layer responds to a first threshold voltage and a first polarity of the electrical signal to generate an oxidation interface between the switching material layer and the oxidation-reduction reversible material layer, and responds to a second threshold voltage and a second polarity of the electrical signal to reduce the generation of the oxidation interface.

Abstract: An electronic device may include a semiconductor memory structured to include a plurality of memory cells, wherein each of the plurality of memory cells may comprise: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple an electrical connection between the first electrode layer and the second electrode layer based on a magnitude of an applied voltage or an applied current with respect to a threshold magnitude, wherein the selection element layer has a dopant concentration profile which decreases from an interface between the selection element layer and the first electrode layer toward an interface between the selection element layer and the second electrode layer.

Abstract: A method for fabricating a semiconductor device may include forming a stopper layer; forming an intermediate pattern material layer over the stopper layer; forming a plurality of first preliminary intermediate patterns by patterning the intermediate pattern material layer; forming a plurality of second preliminary intermediate patterns by shrinking the first preliminary intermediate patterns; forming a conductive material layer to cover the second preliminary intermediate patterns; forming a plurality of preliminary conductive interconnection patterns by patterning the conductive material layer; forming a filling layer between the preliminary conductive interconnection patterns; and forming a plurality of intermediate patterns, a plurality of conductive interconnection patterns and a plurality of filling patterns by removing top portions of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns.

Abstract: A cross-point array device includes a substrate, a first conductive line disposed over the substrate and extending in a first direction, a plurality of pillar structures disposed on the first conductive line, each of the pillar structure comprising a memory electrode, a resistive memory layer disposed along surfaces of the pillar structures, a threshold switching layer disposed on the resistive memory layer, and a second conductive line electrically connected to the threshold switching layer and extending a second direction that is not parallel to the first conductive line.

Abstract: A semiconductor device may include a lower interlayer dielectric layer, a conductive interconnection pattern structure and a filling pattern over the lower interlayer dielectric layer, and a top interlayer dielectric layer over the conductive interconnection pattern structure and the filling patterns. Each of the conductive interconnection pattern structure may include an intermediate pattern in the center thereof, a first conductive interconnection pattern on a first side surface of the intermediate pattern, and a second conductive interconnection pattern on a second side surface of the intermediate pattern. The first conductive interconnection pattern and the second conductive interconnection pattern may have a symmetrical structure to each other.

Abstract: A resistance change memory device is provided. The resistance change memory device includes a lower electrode, a tunneling barrier layer disposed on the lower electrode, a resistance switching layer disposed on the tunneling barrier layer, an oxygen vacancy reservoir layer disposed on the resistance switching layer, and an upper electrode disposed on the oxygen vacancy reservoir layer. The oxygen vacancy reservoir layer is electrically conductive.

Abstract: In a method of reading a resistive memory device according to an embodiment, a memory cell including a selection element and a variable resistance element is prepared. The selection element exhibits a snap-back behavior on a current-voltage sweep curve for the memory cell. First and second read voltages to be applied to the memory cell are determined within a voltage range in which the selection element maintains a turned-on state. The magnitude of the second read voltage is less than that of the first read voltage and selected in a voltage range in which the selection element exhibits the snap-back behavior. The first read voltage is applied to the memory cell to measure a first cell current. The second read voltage is applied to the memory cell to measure a second cell current. A resistance state stored in the memory cell is determined based on the first cell current and the second cell current.

Abstract: A cross-point array device includes a substrate, a first conductive line disposed over the substrate and extending in a first direction, a plurality of pillar structures disposed on the first conductive line, each of the pillar structure comprising a memory electrode, a resistive memory layer disposed along surfaces of the pillar structures, a threshold switching layer disposed on the resistive memory layer, and a second conductive line electrically connected to the threshold switching layer and extending a second direction that is not parallel to the first conductive line.

Abstract: In a method of reading a resistive memory device according to an embodiment, a memory cell including a selection element and a variable resistance element is prepared. The selection element exhibits a snap-back behavior on a current-voltage sweep curve for the memory cell. First and second read voltages to be applied to the memory cell are determined within a voltage range in which the selection element maintains a turned-on state. The magnitude of the second read voltage is less than that of the first read voltage and selected in a voltage range in which the selection element exhibits the snap-back behavior. The first read voltage is applied to the memory cell to measure a first cell current. The second read voltage is applied to the memory cell to measure a second cell current. A resistance state stored in the memory cell is determined based on the first cell current and the second cell current.

Abstract: A switching device includes a first switching element having a snap-back behavior characteristic, an output voltage of the first switching element decreasing when an input current increases from a turn-on threshold current of the first switching element. The switching device further includes a second switching element having a continuous-resistance behavior characteristic, an output voltage of the second switching element increasing when the input current increases from a turn-on threshold current of the second switching element. The turn-on threshold current of the first switching element is lower than the turn-on threshold current of the second switching element.

Abstract: A switching device includes a first switching element having a snap-back behavior characteristic, an output voltage of the first switching element decreasing when an input current increases from a turn-on threshold current of the first switching element. The switching device further includes a second switching element having a continuous-resistance behavior characteristic, an output voltage of the second switching element increasing when the input current increases from a turn-on threshold current of the second switching element. The turn-on threshold current of the first switching element is lower than the turn-on threshold current of the second switching element.

Abstract: A resistance change memory device is provided. The resistance change memory device includes a lower electrode, a tunneling barrier layer disposed on the lower electrode, a resistance switching layer disposed on the tunneling barrier layer, an oxygen vacancy reservoir layer disposed on the resistance switching layer, and an upper electrode disposed on the oxygen vacancy reservoir layer. The oxygen vacancy reservoir layer is electrically conductive.

Abstract: A resistive random access memory device is provided. The resistive random access memory device includes a first electrode, a second electrode, and an electrolyte layer disposed between the first electrode and the second electrode. One of the first electrode and the second electrode includes an ion supply layer providing two or more kinds of metal ions to the electrolyte layer. The two or more kinds of metal ions have different mobilities in the electrolyte layer. Two or more conductive bridges are generated by the two or more kinds of metal ions, respectively.

Abstract: A method of manufacturing a switching element includes forming a first electrode layer over a substrate, forming a switching structure on the first electrode layer, and forming a second electrode layer on the switching structure. The switching structure includes a plurality of unit switching layers that includes a first unit switching layer and a second unit switching layer. Forming the first unit switching layer includes forming a first unit insulation layer, and injecting first dopants into the first unit insulation layer by performing a first ion implantation process. Forming the second unit switching layer includes forming a second unit insulation layer, and injecting second dopants into the second unit insulation layer by performing a second implantation process.

Abstract: A method of sensing a resistance change memory device includes preparing a memory cell including a variable resistance element storing different data on the basis of a variable resistance, and a switching element connected to the variable resistance element and performing a threshold switching operation, measuring a first cell current by applying a first read voltage to the memory cell, the first read voltage being selected in a threshold-sensing range of a current-voltage characteristic curve of the memory cell, measuring a second cell current by applying a second read voltage to the memory cell, the second read voltage being selected in a resistance-sensing range of the current-voltage characteristic curve, and when at least one of the first cell current and the second cell current is greater than a corresponding reference current, outputting a data signal having a first logic value as data stored in the memory cell.

Abstract: An electronic device includes a transistor. The transistor includes a body including a metal oxide; a gate electrode; and a gate insulating layer interposed between the body and the gate electrode, wherein the transistor is turned on or turned off by movement of oxygen vacancies in the body according to voltages applied to the gate electrode and the body.

Abstract: A method of sensing a resistance change memory device includes preparing a memory cell including a variable resistance element storing different data on the basis of a variable resistance, and a switching element connected to the variable resistance element and performing a threshold switching operation, measuring a first cell current by applying a first read voltage to the memory cell, the first read voltage being selected in a threshold-sensing range of a current-voltage characteristic curve of the memory cell, measuring a second cell current by applying a second read voltage to the memory cell, the second read voltage being selected in a resistance-sensing range of the current-voltage characteristic curve, and when at least one of the first cell current and the second cell current is greater than a corresponding reference current, outputting a data signal having a first logic value as data stored in the memory cell.

Abstract: A resistive random access memory device is provided. The resistive random access memory device includes a first electrode, a second electrode, and an electrolyte layer disposed between the first electrode and the second electrode. One of the first electrode and the second electrode includes an ion supply layer providing two or more kinds of metal ions to the electrolyte layer. The two or more kinds of metal ions have different mobilities in the electrolyte layer. Two or more conductive bridges are generated by the two or more kinds of metal ions, respectively.

Abstract: A method of manufacturing a switching element includes forming a first electrode layer over a substrate, forming a switching structure on the first electrode layer, and forming a second electrode layer on the switching structure. The switching structure includes a plurality of unit switching layers that includes a first unit switching layer and a second unit switching layer. Forming the first unit switching layer includes forming a first unit insulation layer, and injecting first dopants into the first unit insulation layer by performing a first ion implantation process. Forming the second unit switching layer includes forming a second unit insulation layer, and injecting second dopants into the second unit insulation layer by performing a second implantation process.

Abstract: An electronic device includes a transistor. The transistor includes a body including a metal oxide; a gate electrode; and a gate insulating layer interposed between the body and the gate electrode, wherein the transistor is turned on or turned off by movement of oxygen vacancies in the body according to voltages applied to the gate electrode and the body.