Abstract: A method of making a semiconductor device involves the steps of disposing a first semiconductor die over a substrate and disposing a beam homogenizer over the first semiconductor die. A beam from the beam homogenizer impacts the first semiconductor die. The method further includes the steps of determining a positional offset of the beam relative to the first semiconductor die in a number of pixels, using a first calibration equation to convert the number of pixels into a distance in millimeters, and moving the beam homogenizer the distance in millimeters to align the beam and first semiconductor die.

Abstract: A semiconductor device has a semiconductor die, substrate, and plurality of first conductive pillars formed over the semiconductor die or substrate. Alternatively, the first conductive pillars formed over the semiconductor die and substrate. An electrical component is disposed over the semiconductor die. The electrical component can be a double-sided IPD. The semiconductor die and electrical component are disposed over the substrate. A shielding frame is disposed over the semiconductor die. A plurality of second conductive pillars is formed over a first surface of the electrical component. A plurality of third conductive pillars is formed over a second surface of the electrical component opposite the first surface of the electrical component. A bump cap can be formed over a distal end of the conductive pillars. The substrate has a cavity and the electrical component is disposed within the cavity. An underfill material is deposited between the semiconductor die and substrate.

Abstract: A semiconductor device has a substrate and a first semiconductor die disposed over the substrate. A subpackage is also disposed over the substrate. A stiffener is disposed over the substrate around the first semiconductor die and subpackage. A heat spreader is disposed over the stiffener. The heat spreader is thermally coupled to the first semiconductor die. The heat spreader has an opening over the subpackage.

Abstract: A semiconductor device has an electrical component and a first TIM with a first compliant property is disposed over a surface of the electrical component. A second TIM having a second compliant property greater than the first compliant property is disposed over the surface of the electrical component within the first TIM. A third TIM can be disposed over the surface of the electrical component along the first TIM. A heat sink is disposed over the first TIM and second TIM. The second TIM has a shape of a star pattern, grid of dots, parallel lines, serpentine, or concentric geometric shapes. The first TIM provides adhesion for joint reliability and the second TIM provides stress relief. Alternatively, a heat spreader is disposed over the first TIM and second TIM and a heat sink is disposed over a third TIM and fourth TIM on the heat spreader.

Abstract: A semiconductor device has an electrical component and a first TIM with a first compliant property is disposed over a surface of the electrical component. A second TIM having a second compliant property greater than the first compliant property is disposed over the surface of the electrical component within the first TIM. A third TIM can be disposed over the surface of the electrical component along the first TIM. A heat sink is disposed over the first TIM and second TIM. The second TIM has a shape of a star pattern, grid of dots, parallel lines, serpentine, or concentric geometric shapes. The first TIM provides adhesion for joint reliability and the second TIM provides stress relief. Alternatively, a heat spreader is disposed over the first TIM and second TIM and a heat sink is disposed over a third TIM and fourth TIM on the heat spreader.

Abstract: A display device according to one aspect of the present disclosure includes: a substrate including a display area and a non-display area enclosing the display area; a plurality of pixels disposed in the display area; and a gate driving unit disposed in the non-display area on both sides of the display area and including a plurality of stages. The plurality of stages includes a plurality of normal output stages and a plurality of dummy stages which does not output a signal. The plurality of dummy stages may be connected to a gate low voltage line.

Abstract: A semiconductor device has a substrate and a first semiconductor die disposed over the substrate. A subpackage is also disposed over the substrate. A stiffener is disposed over the substrate around the first semiconductor die and subpackage. A heat spreader is disposed over the stiffener. The heat spreader is thermally coupled to the first semiconductor die. The heat spreader has an opening over the subpackage.

Abstract: A semiconductor device has an electrical component and a first TIM with a first compliant property is disposed over a surface of the electrical component. A second TIM having a second compliant property greater than the first compliant property is disposed over the surface of the electrical component within the first TIM. A third TIM can be disposed over the surface of the electrical component along the first TIM. A heat sink is disposed over the first TIM and second TIM. The second TIM has a shape of a star pattern, grid of dots, parallel lines, serpentine, or concentric geometric shapes. The first TIM provides adhesion for joint reliability and the second TIM provides stress relief. Alternatively, a heat spreader is disposed over the first TIM and second TIM and a heat sink is disposed over a third TIM and fourth TIM on the heat spreader.

Abstract: A method of making a semiconductor device involves the steps of disposing a first semiconductor die over a substrate and disposing a beam homogenizer over the first semiconductor die. A beam from the beam homogenizer impacts the first semiconductor die. The method further includes the steps of determining a positional offset of the beam relative to the first semiconductor die in a number of pixels, using a first calibration equation to convert the number of pixels into a distance in millimeters, and moving the beam homogenizer the distance in millimeters to align the beam and first semiconductor die.

Abstract: Disclosed herein is a display device for increasing the transmittance of R, G, and B sub-pixels and reducing a transmittance of W sub-pixel through a pixel asymmetric design. To this end, the display device has a pixel asymmetric structure in which W sub-pixel has a different area from R, G and B sub-pixels. As a result, as the display device has an asymmetric structure in which the areas of W, R, G, and B sub-pixels are different from one another, particularly, an asymmetric structure in which the area of W sub-pixel is reduced and the area of R sub-pixel is increased. Such design has a structural advantage that the transmittance of R, G, and B sub-pixels can be increased and the transmittance of W sub-pixel can be lowered so that it is possible to correspond the product specifications in various ways.

Abstract: A display panel is provided having a built-in touchscreen and a touch display device including the same. The display panel has a touch electrode structure allowing parasitic capacitance to be dispersed to a greater number of gate lines, which form parasitic capacitance together with touch electrodes, without concentrically relying on specific gate lines. Differences in load between gate lines are reduced to improve image quality.

Abstract: Disclosed herein is a display device designed to increase the transmittance of R, G, and B sub-pixels and to reduce a transmittance of W sub-pixel through a pixel asymmetric design in order to correspond to the product specifications. To this end, the display device according to the present disclosure has a pixel asymmetric structure in which W sub-pixel is designed to have a different area from R, G and B sub-pixels. As a result, as the display device according to the present disclosure has an asymmetric structure in which the areas of W, R, G, and B sub-pixels are different from one another, particularly, an asymmetric structure in which the area of W sub-pixel is reduced and the area of R sub-pixel is increased, it has a structural advantage that the transmittance of R, G, and B sub-pixels can be increased and the transmittance of W sub-pixel can be lowered so that it is possible to correspond the product specifications in various ways.

Abstract: Disclosed is an in-cell touch liquid crystal display (LCD) apparatus comprising: an active area in which a plurality of pixels are provided; and a pad area in which an auto probe test pattern is disposed, wherein the auto probe test pattern comprises a common voltage enable signal line; a common voltage switching unit; a data enable signal line through which a data enable signal is applied; and a data switching unit that is coupled to the data enable signal line and configured to be turned on by the data enable signal and output a data voltage. The common voltage enable signal line and the data enable signal line are disposed separately from each other.

Abstract: A display panel is provided having a built-in touchscreen and a touch display device including the same. The display panel has a touch electrode structure allowing parasitic capacitance to be dispersed to a greater number of gate lines, which form parasitic capacitance together with touch electrodes, without concentrically relying on specific gate lines. Differences in load between gate lines are reduced to improve image quality.

Abstract: Disclosed is an in-cell touch liquid crystal display (LCD) apparatus comprising: an active area in which a plurality of pixels are provided; and a pad area in which an auto probe test pattern is disposed, wherein the auto probe test pattern comprises a common voltage enable signal line; a common voltage switching unit; a data enable signal line through which a data enable signal is applied; and a data switching unit that is coupled to the data enable signal line and configured to be turned on by the data enable signal and output a data voltage. The common voltage enable signal line and the data enable signal line are disposed separately from each other.

Abstract: A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR?2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped.

Abstract: A plastic ball grid array semiconductor package employs a metal heat spreader having supporting arms embedded in the molding cap, in which the embedded supporting arms are not directly affixed to the substrate or in which any supporting arm that is affixed to the substrate is affixed using a resilient material such as an elastomeric adhesive. Also, a process for forming the package includes steps of placing the heat spreader in a mold cavity, placing the substrate over the mold cavity such that the die support surface of the substrate contacts the supporting arms of the heat spreader, and injecting the molding material into the cavity to form the molding cap. The substrate is positioned in register over the mold cavity such that as the molding material hardens to form the mold cap the embedded heat spreader becomes fixed in the appropriate position in relation to the substrate.

Abstract: A semiconductor device is made by disposing a film layer over a substrate having first conductive layer. An opening is formed in the film layer to expose the first conductive layer. A second conductive layer is formed over the first conductive layer. A first bump is formed over the second conductive layer which promotes reflow of the first bump at a eutectic temperature. A standoff bump is formed on the film layer around a perimeter of the substrate. The film layer prevents reflow of the standoff bump at the eutectic temperature. A second bump is disposed between a semiconductor die and the first bump. The second bump is reflowed to electrically connect the semiconductor die to the first bump. After reflow of the second bump, the standoff bump has a height at least 70% of the second bump prior to reflow to maintain separation between the semiconductor die and substrate.

Abstract: A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR?2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped.

Abstract: A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR?2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped.