Abstract: An electronic device includes a substrate having a conductive structure with a substrate outward terminal at a second side of the substrate. A dielectric structure with an opening is adjacent to the second side. An electronic component is coupled to the substrate and an encapsulant encapsulates the electronic component. The substrate outward terminal comprises a multi-via terminal or a multi-stage via. The multi-via terminal includes pad conductive vias in the opening, a pad dielectric via interposed between the pad conductive vias, and a conductor comprising a conductor top side with micro dimples over the pad conductive vias and the pad dielectric via. The multi-stage terminal includes a pad base within the opening having a top side recessed below an upper surface the dielectric and a pad head coupled to the pad base within the opening, the pad head having a top side with a micro dimple.

Abstract: In one example, a semiconductor device comprises a redistribution layer (RDL) substrate having a top surface and a bottom surface, wherein the RDL substrate comprises a filler-free dielectric material, an electronic device on the top surface of the RDL substrate, an electrical interconnect on the bottom surface of the RDL substrate and electrically coupled to the electronic device, a first protective material contacting a side surface of the electronic device and the top surface of the RDL substrate, and a second protective material contacting a side surface of the electrical interconnect and the bottom surface of the RDL substrate. Other examples and related methods are also disclosed herein.

Abstract: A printed circuit board according to an embodiment includes an insulating layer; a first pad disposed on an upper surface of the insulating layer; a second pad disposed on a lower surface of the insulating layer; a first device mounted on the first pad; a second device mounted on the second pad; a first molding layer disposed on the insulating layer and molding the first device; and a second molding layer disposed on the lower surface of the insulating layer and molding the second device, wherein a lower surface of the second molding layer is positioned on the same plane as a lower surface of the second device.

Abstract: A printed circuit board according to an embodiment includes an insulating layer; a first pad disposed on an upper surface of the insulating layer; a second pad disposed on a lower surface of the insulating layer; a first device mounted on the first pad; a second device mounted on the second pad; a first molding layer disposed on the insulating layer and molding the first device; and a second molding layer disposed on the lower surface of the insulating layer and molding the second device, wherein a lower surface of the second molding layer is positioned on the same plane as a lower surface of the second device.

Abstract: In one example, a semiconductor device comprises a redistribution layer (RDL) substrate having a top surface and a bottom surface, wherein the RDL substrate comprises a filler-free dielectric material, an electronic device on the top surface of the RDL substrate, an electrical interconnect on the bottom surface of the RDL substrate and electrically coupled to the electronic device, a first protective material contacting a side surface of the electronic device and the top surface of the RDL substrate, and a second protective material contacting a side surface of the electrical interconnect and the bottom surface of the RDL substrate. Other examples and related methods are also disclosed herein.

Abstract: An electronic device includes a substrate having a conductive structure with a substrate outward terminal at a second side of the substrate. A dielectric structure with an opening is adjacent to the second side. An electronic component is coupled to the substrate and an encapsulant encapsulates the electronic component. The substrate outward terminal comprises a multi-via terminal or a multi-stage via. The multi-via terminal includes pad conductive vias in the opening, a pad dielectric via interposed between the pad conductive vias, and a conductor comprising a conductor top side with micro dimples over the pad conductive vias and the pad dielectric via. The multi-stage terminal includes a pad base within the opening having a top side recessed below an upper surface the dielectric and a pad head coupled to the pad base within the opening, the pad head having a top side with a micro dimple.

Abstract: In one example, an electronic device includes a substrate having a conductive structure. The conductive structure includes a substrate inward terminal at a first side of the substrate and a substrate outward terminal at a second side of the substrate. The substrate includes a dielectric structure with a first opening is at the second side. An electronic component is at the first side of the substrate and is electrically coupled to the substrate inward terminal, and an encapsulant encapsulates the electronic component. The substrate outward terminal comprises one of a multi-via terminal or a multi-stage via. The multi-via terminal includes pad conductive vias in the first opening a pad dielectric via interposed between the pad conductive vias in the first opening and a conductor comprising a conductor top side with micro dimples over the pad conductive vias and the pad dielectric via.

Abstract: A circuit board according to an embodiment includes an insulating layer; a circuit pattern disposed on an upper surface of the insulating layer; a first solder resist disposed on an upper surface of the insulating layer and having a height smaller than a height of the circuit pattern; and a second solder resist disposed on an upper surface of the first solder resist and including a first portion having an upper surface lower than an upper surface of the circuit pattern and a second portion having an upper surface higher than the upper surface of the circuit pattern, wherein the circuit pattern includes: a plurality of first circuit patterns disposed on an upper surface of a first region of the insulating layer, and a plurality of second circuit patterns disposed on an upper surface of a second region of the insulating layer; wherein the first portion of the second solder resist is disposed between the plurality of first circuit patterns to have an upper surface lower than an upper surface of the first circuit

Abstract: A circuit board according to an embodiment includes an insulating layer; a circuit pattern disposed on an upper surface of the insulating layer; a first solder resist disposed on an upper surface of the insulating layer and having a height smaller than a height of the circuit pattern; and a second solder resist disposed on an upper surface of the first solder resist and including a first portion having an upper surface lower than an upper surface of the circuit pattern and a second.

Abstract: A printed circuit board according to an embodiment includes an insulating layer; a first pad disposed on an upper surface of the insulating layer; a second pad disposed on a lower surface of the insulating layer; a first device mounted on the first pad; a second device mounted on the second pad; a first molding layer disposed on the insulating layer and molding the first device; and a second molding layer disposed on the lower surface of the insulating layer and molding the second device, wherein a lower surface of the second molding layer is positioned on the same plane as a lower surface of the second device.

Abstract: In one example, a semiconductor device comprises a redistribution layer (RDL) substrate having a top surface and a bottom surface, wherein the RDL substrate comprises a filler-free dielectric material, an electronic device on the top surface of the RDL substrate, an electrical interconnect on the bottom surface of the RDL substrate and electrically coupled to the electronic device, a first protective material contacting a side surface of the electronic device and the top surface of the RDL substrate, and a second protective material contacting a side surface of the electrical interconnect and the bottom surface of the RDL substrate. Other examples and related methods are also disclosed herein.

Abstract: In one example, an electronic device includes a substrate having a conductive structure. The conductive structure includes a substrate inward terminal at a first side of the substrate and a substrate outward terminal at a second side of the substrate. The substrate includes a dielectric structure with a first opening is at the second side. An electronic component is at the first side of the substrate and is electrically coupled to the substrate inward terminal, and an encapsulant encapsulates the electronic component. The substrate outward terminal comprises one of a multi-via terminal or a multi-stage via. The multi-via terminal includes pad conductive vias in the first opening a pad dielectric via interposed between the pad conductive vias in the first opening and a conductor comprising a conductor top side with micro dimples over the pad conductive vias and the pad dielectric via.

Abstract: In one example, a semiconductor device comprises a redistribution layer (RDL) substrate having a top surface and a bottom surface, wherein the RDL substrate comprises a filler-free dielectric material, an electronic device on the top surface of the RDL substrate, an electrical interconnect on the bottom surface of the RDL substrate and electrically coupled to the electronic device, a first protective material contacting a side surface of the electronic device and the top surface of the RDL substrate, and a second protective material contacting a side surface of the electrical interconnect and the bottom surface of the RDL substrate. Other examples and related methods are also disclosed herein.

Abstract: Disclosed is a light emitting device according to the embodiment including a conductive semiconductor layer divided into at least two or more light emitting regions; a plurality of light emitting structures on the conductive semiconductor layer; an electrode layer on the plurality of light emitting structures; a second electrode electrically connected to the electrode layer; and a first electrode electrically connected to the conductive semiconductor layer, wherein each of the light emitting structures includes a rod-shaped first conductivity type semiconductor, an active layer configured to surround the first conductivity type semiconductor and a second conductivity type semiconductor configured to surround the active layer, and each of the light emitting structures has at least two or more outer surfaces having different extending directions with respect to an upper surface of the conductive semiconductor layer.

Abstract: In one embodiment, an electronic package includes a substrate having a die pad plurality of lands embedded within substrate encapsulant. An electronic chip including an electronic component is connected to the die pad. The die pad is configured with a recessed well extending from a top surface of the die pad towards a bottom surface of the die pad. The electronic component is position at least proximate to and overlapping the recessed well to increase the distance between the die pad and the electronic component. In one embodiment, the electronic component includes a passive component, such as an inductor. A package body encapsulates the electronic chip and top surfaces of the substrate, and is further disposed within the recessed well. The die pad bottom surface is continuous below the recessed well.

Abstract: In one embodiment, a semiconductor device includes a single layer substrate having an insulation layer and conductive patterns on a first surface of the insulation layer. A semiconductor die is attached on a first surface of the single layer substrate and electrically connected to the conductive patterns. Conductive bumps are also on the first surface of the single layer substrate and electrically connected to the semiconductor die through the conductive patterns. An encapsulant overlaps at least portions of the first surface of the single layer substrate. The conductive bumps are at least partially exposed in the encapsulant.

Abstract: In one embodiment, an electronic package includes a substrate having a die pad plurality of lands embedded within substrate encapsulant. An electronic chip including an electronic component is connected to the die pad. The die pad is configured with a recessed well extending from a top surface of the die pad towards a bottom surface of the die pad. The electronic component is position at least proximate to and overlapping the recessed well to increase the distance between the die pad and the electronic component. In one embodiment, the electronic component includes a passive component, such as an inductor. A package body encapsulates the electronic chip and top surfaces of the substrate, and is further disposed within the recessed well. The die pad bottom surface is continuous below the recessed well.

Abstract: In one embodiment, a semiconductor device includes a single layer substrate having an insulation layer and conductive patterns on a first surface of the insulation layer. A semiconductor die is attached on a first surface of the single layer substrate and electrically connected to the conductive patterns. Conductive bumps are also on the first surface of the single layer substrate and electrically connected to the semiconductor die through the conductive patterns. An encapsulant overlaps at least portions of the first surface of the single layer substrate. The conductive bumps are at least partially exposed in the encapsulant.

Abstract: The invention relates to an embroidering machine in which a moving body (40) is installed on a base framework (10) so as to be displaceable along a Y-axis, a sewing device (60) is installed on the moving body (40) so as to be displaceable along an X-axis by LM guides (61,62) and a ball screw (63) connected to a motor (64), and longitudinally elongated left and right nippers (70, 80) are installed on opposite sides of the base framework (10) to keep a cloth tensioned along the X-axis until a predetermined unit size of cloth fed to the base framework (10) is completely embroidered.