Abstract: A method of fabricating an a non-volatile memory includes forming trench isolation regions in an inactive region of a semiconductor substrate, adjacent trench isolation regions defining respective protrusions having rounded edges therebetween, wherein upper surfaces of the trench isolation regions are lower than an upper surface of the semiconductor substrate and wherein the protrusions define an active region, forming a tunnel insulating layer covering the protrusion of the semiconductor substrate, and forming, sequentially, a storage layer, a blocking insulating layer, and a gate layer covering the tunnel insulating layer.

Abstract: An electrically erasable programmable read-only memory (EEPROM) comprises trench isolation regions whose upper surfaces are recessed compared with an upper surface of the semiconductor substrate, thereby allowing use of all surfaces of a protrusion of the semiconductor substrate between the isolation regions, including the upper surface of the semiconductor substrate, as an active region. Accordingly, the performance of a memory cell can be improved by increasing the size of an active channel region without needing to change the size of a planar unit cell.

Abstract: Nonvolatile memory devices and methods for fabricating the same are provided. The device includes first and second base patterns disposed under floating and selection gates, respectively, at an active region. A channel region is formed in the active region between the first and second base patterns, and source and drain regions are formed in the active region adjacent to the first and second base patterns, respectively. The method includes forming first and second base patterns on a semiconductor substrate to be separated from each other by a predetermined space. A channel region is formed in the semiconductor substrate between the first and second base patterns. Source and drain regions are formed in the semiconductor substrate adjacent to the reverse side of the channel region on the basis of the first and second base patterns, respectively. A tunnel oxide layer is formed on a predetermined region of the channel region. A memory gate is formed to cover the first base pattern and the tunnel oxide layer.

Abstract: A method of fabricating an a non-volatile memory includes forming trench isolation regions in an inactive region of a semiconductor substrate, adjacent trench isolation regions defining respective protrusions having rounded edges therebetween, wherein upper surfaces of the trench isolation regions are lower than an upper surface of the semiconductor substrate and wherein the protrusions define an active region, forming a tunnel insulating layer covering the protrusion of the semiconductor substrate, and forming, sequentially, a storage layer, a blocking insulating layer, and a gate layer covering the tunnel insulating layer.

Abstract: An electrically erasable programmable read-only memory (EEPROM) comprises trench isolation regions whose upper surfaces are recessed compared with an upper surface of the semiconductor substrate, thereby allowing use of all surfaces of a protrusion of the semiconductor substrate between the isolation regions, including the upper surface of the semiconductor substrate, as an active region. Accordingly, the performance of a memory cell can be improved by increasing the size of an active channel region without needing to change the size of a planar unit cell.

Abstract: An electrically erasable programmable read-only memory (EEPROM) comprises trench isolation regions whose upper surfaces are recessed compared with an upper surface of the semiconductor substrate, thereby allowing use of all surfaces of a protrusion of the semiconductor substrate between the isolation regions, including the upper surface of the semiconductor substrate, as an active region. Accordingly, the performance of a memory cell can be improved by increasing the size of an active channel region without needing to change the size of a planar unit cell.

Abstract: Nonvolatile memory devices and methods for fabricating the same are provided. The device includes first and second base patterns disposed under floating and selection gates, respectively, at an active region. A channel region is formed in the active region between the first and second base patterns, and source and drain regions are formed in the active region adjacent to the first and second base patterns, respectively. The method includes forming first and second base patterns on a semiconductor substrate to be separated from each other by a predetermined space. A channel region is formed in the semiconductor substrate between the first and second base patterns. Source and drain regions are formed in the semiconductor substrate adjacent to the reverse side of the channel region on the basis of the first and second base patterns, respectively. A tunnel oxide layer is formed on a predetermined region of the channel region. A memory gate is formed to cover the first base pattern and the tunnel oxide layer.

Abstract: Nonvolatile memory devices and methods for fabricating the same are provided. The device includes first and second base patterns disposed under floating and selection gates, respectively, at an active region. A channel region is formed in the active region between the first and second base patterns, and source and drain regions are formed in the active region adjacent to the first and second base patterns, respectively. The method includes forming first and second base patterns on a semiconductor substrate to be separated from each other by a predetermined space. A channel region is formed in the semiconductor substrate between the first and second base patterns. Source and drain regions are formed in the semiconductor substrate adjacent to the reverse side of the channel region on the basis of the first and second base patterns, respectively. A tunnel oxide layer is formed on a predetermined region of the channel region. A memory gate is formed to cover the first base pattern and the tunnel oxide layer.

Abstract: An electrically erasable programmable read-only memory (EEPROM) comprises trench isolation regions whose upper surfaces are recessed compared with an upper surface of the semiconductor substrate, thereby allowing use of all surfaces of a protrusion of the semiconductor substrate between the isolation regions, including the upper surface of the semiconductor substrate, as an active region. Accordingly, the performance of a memory cell can be improved by increasing the size of an active channel region without needing to change the size of a planar unit cell.

Abstract: Nonvolatile memory devices and methods for fabricating the same are provided. The device includes first and second base patterns disposed under floating and selection gates, respectively, at an active region. A channel region is formed in the active region between the first and second base patterns, and source and drain regions are formed in the active region adjacent to the first and second base patterns, respectively. The method includes forming first and second base patterns on a semiconductor substrate to be separated from each other by a predetermined space. A channel region is formed in the semiconductor substrate between the first and second base patterns. Source and drain regions are formed in the semiconductor substrate adjacent to the reverse side of the channel region on the basis of the first and second base patterns, respectively. A tunnel oxide layer is formed on a predetermined region of the channel region. A memory gate is formed to cover the first base pattern and the tunnel oxide layer.