Patents by Inventor Tae-Kwon Lee

Tae-Kwon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10982695
    Abstract: Provided are embodiments of a pressure-compensated load transfer device that includes a plate having a first shaft vertically installed on one side and a second shaft vertically installed on the other side to be coaxial with the first shaft. Also included is a first bellows having an opening in one side to surround the first shaft, with the other side thereof being fixed to the one side of the plate. Further included is a plurality of second bellows each having an opening in one end, with the other end thereof being attached to the other side of the plate. A housing is also included, and the housing includes a high-pressure working hole communicating with the opening of the first bellows and a high-pressure channel coplanar with the high-pressure working hole and communicating with the openings of the second bellows. The plate is back-and-forth movably received in the housing.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: April 20, 2021
    Assignee: Kepco Nuclear Fuel Co., Ltd.
    Inventors: Kyoung-hong Kim, Jin-seon Kim, Jong-sung Yoo, Kyeong-lak Jeon, Kyong-bo Eom, Joon-kyoo Park, Young-ik Yoo, Oh-joon Kwon, Joong-jin Kim, Tae-kwon Lee
  • Publication number: 20190145436
    Abstract: Provided are embodiments of a pressure-compensated load transfer device that includes a plate having a first shaft vertically installed on one side and a second shaft vertically installed on the other side to be coaxial with the first shaft. Also included is a first bellows having an opening in one side to surround the first shaft, with the other side thereof being fixed to the one side of the plate. Further included is a plurality of second bellows each having an opening in one end, with the other end thereof being attached to the other side of the plate. A housing is also included, and the housing includes a high-pressure working hole communicating with the opening of the first bellows and a high-pressure channel coplanar with the high-pressure working hole and communicating with the openings of the second bellows. The plate is back-and-forth movably received in the housing.
    Type: Application
    Filed: January 11, 2019
    Publication date: May 16, 2019
    Applicant: KEPCO NUCLEAR FUEL CO., LTD.
    Inventors: Kyoung-hong Kim, Jin-seon Kim, Jong-sung Yoo, Kyeong-lak Jeon, Kyong-bo Eom, Joon-kyoo Park, Young-ik Yoo, Oh-joon Kwon, Joong-jin Kim, Tae-kwon Lee
  • Publication number: 20120302447
    Abstract: The present invention describes a method of measurement of pyrosequencing accuracy by directly calculating sequence errors from FLX Titanium pyrosequencing using mock community, according to the present invention, sequencing errors from FLX Titanium pyrosequencing in terms of microbial diversity and classification can be measured, resulting in possible effects of filtering.
    Type: Application
    Filed: February 22, 2012
    Publication date: November 29, 2012
    Inventors: Joon-Hong Park, Tae-Kwon Lee
  • Patent number: 7868458
    Abstract: The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer; an epitaxially grown titanium silicide layer having a phase of C49 and formed on the exposed silicon substrate disposed within the contact hole; and a metal layer formed on an upper surface of the titanium silicide layer.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: January 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Moon-Keun Lee, Tae-Kwon Lee, Jun-Mo Yang, Tae-Su Park, Yoon-Jik Lee
  • Patent number: 7825014
    Abstract: A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed at a given temperature for a given period of time in a manner that a reaction between the first layer and the nitrogen used when forming the second layer is controlled.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 2, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Min-Gyu Sung, Hong-Seon Yang, Tae-Kwon Lee, Won Kim, Kwan-Yong Lim, Seung-Ryong Lee
  • Publication number: 20090146306
    Abstract: The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer; an epitaxially grown titanium silicide layer having a phase of C49 and formed on the exposed silicon substrate disposed within the contact hole; and a metal layer formed on an upper surface of the titanium silicide layer.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 11, 2009
    Inventors: Moon-Keun Lee, Tae-Kwon Lee, Jun-Mo Yang, Tae-Su Park, Yoon-Jik Lee
  • Publication number: 20090111256
    Abstract: A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed at a given temperature for a given period of time in a manner that a reaction between the first layer and the nitrogen used when forming the second layer is controlled.
    Type: Application
    Filed: June 30, 2008
    Publication date: April 30, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Min-Gyu SUNG, Hong-Seon Yang, Tae-Kwon Lee, Won Kim, Kwan-Yong Lim, Seung-Ryong Lee
  • Patent number: 7476617
    Abstract: The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer; an epitaxially grown titanium silicide layer having a phase of C49 and formed on the exposed silicon substrate disposed within the contact hole; and a metal layer formed on an upper surface of the titanium silicide layer.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: January 13, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Moon-Keun Lee, Tae-Kwon Lee, Jun-Mo Yang, Tae-Su Park, Yoon-Jik Lee
  • Publication number: 20060157742
    Abstract: The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer; an epitaxially grown titanium silicide layer having a phase of C49 and formed on the exposed silicon substrate disposed within the contact hole; and a metal layer formed on an upper surface of the titanium silicide layer.
    Type: Application
    Filed: February 24, 2006
    Publication date: July 20, 2006
    Inventors: Moon-Keun Lee, Tae-Kwon Lee, Jun-Mo Yang, Tae-Su Park, Yoon-Jik Lee
  • Patent number: 7037827
    Abstract: A semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. The titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer. An epitaxially grown titanium silicide layer having a phase of C49 and is formed on the exposed silicon substrate disposed within the contact hole; and a metal layer is formed on an upper surface of the titanium silicide layer.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: May 2, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Moon-Keun Lee, Tae-Kwon Lee, Jun-Mo Yang, Tae-Su Park, Yoon-Jik Lee
  • Publication number: 20040180543
    Abstract: A semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. The titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer. An epitaxially grown titanium silicide layer having a phase of C49 and is formed on the exposed silicon substrate disposed within the contact hole; and a metal layer is formed on an upper surface of the titanium silicide layer.
    Type: Application
    Filed: December 30, 2003
    Publication date: September 16, 2004
    Inventors: Moon-Keun Lee, Tae-Kwon Lee, Jun-Mo Yang, Tae-Su Park, Yoon-Jik Lee