Abstract: A data storage device in accordance with an embodiment may include a controller and a memory device. The controller is configured to output a read control signal including an option number related to a read condition. The memory device is configured to perform a read operation based on a read condition corresponding to the option number in response to the read control signal. The read condition for the option number is configured to be stored in a read condition table storage circuit included in the memory device.

Abstract: A data storage device in accordance with an embodiment may include a controller configured to output a read control signal including an option number related to a read condition, and a memory device including a read condition table storage circuit, wherein the read condition table storage circuit is configured to store the read condition for the option number, and wherein the memory device is configured to perform a read operation under a read condition corresponding to the option number in response to the read control signal.

Abstract: A data storage device may include a storage that store data in a plurality of physical storage spaces to which physical addresses are assigned, respectively, and a controller that control the storage, wherein the controller includes a mapping table of the physical addresses corresponding to logical addresses managed by a host, and wherein the controller is further configured to read data, in a primary read operation, from a physical storage space of a physical address corresponding to a logical address requested to be read by the host among the plurality of physical storage spaces according to the mapping table, obtain a normal physical address corresponding to the logical address requested to be read through the mapping table when the data read in the primary read operation is erased data; and read data, in a secondary read operation, from a physical storage space of the normal physical address.

Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller may include a power application timer configured to measure each of plural final power application times, each final power application time being a period of time during which power is applied to the memory controller until the memory controller is turned off after being turned on, and a command blocker configured to disable a set command, among commands that are input from a host to the memory controller depending on a cumulative power application time obtained by accumulating the plural final power application times.

Abstract: A data storage device includes a nonvolatile memory device including a plurality of memory blocks; a random-access memory including a bad block management module configured to register and manage bad blocks included in the plurality of memory blocks; and a processor configured to detect primary bad blocks by performing a primary bad block scan operation on the plurality of memory blocks using the bad block management module, detect secondary bad blocks by performing a secondary bad block scan operation on normal memory blocks other than the primary bad blocks among the plurality of memory blocks, and register the detected primary bad blocks and the detected secondary bad blocks as bad blocks.

Abstract: A data storage device includes a nonvolatile memory apparatus including a plurality of memory blocks, and a controller configured to control the nonvolatile memory apparatus. The controller determines update frequency for data stored in first memory blocks of the plurality of memory blocks, controls the nonvolatile memory apparatus to store target data of the data stored in the plurality of memory blocks in second memory blocks, of the plurality of memory blocks, the target data indicating data having the update frequency exceeding preset threshold update frequency, sets garbage collection execution conditions of the first memory blocks and the second memory blocks to be different from each other, and controls the nonvolatile memory apparatus to perform garbage collection for the first memory blocks and the second memory blocks according to the garbage collection execution conditions set to be different from each other.

Abstract: A data storage device may include a storage that store data in a plurality of physical storage spaces to which physical addresses are assigned, respectively, and a controller that control the storage, wherein the controller includes a mapping table of the physical addresses corresponding to logical addresses managed by a host, and wherein the controller is further configured to read data, in a primary read operation, from a physical storage space of a physical address corresponding to a logical address requested to be read by the host among the plurality of physical storage spaces according to the mapping table, obtain a normal physical address corresponding to the logical address requested to be read through the mapping table when the data read in the primary read operation is erased data; and read data, in a secondary read operation, from a physical storage space of the normal physical address.

Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller may include a power application timer configured to measure each of plural final power application times, each final power application time being a period of time during which power is applied to the memory controller until the memory controller is turned off after being turned on, and a command blocker configured to disable a set command, among commands that are input from a host to the memory controller depending on a cumulative power application time obtained by accumulating the plural final power application times.

Abstract: A data storage device includes a nonvolatile memory device including a plurality of memory blocks; a random-access memory including a bad block management module configured to register and manage bad blocks included in the plurality of memory blocks; and a processor configured to detect primary bad blocks by performing a primary bad block scan operation on the plurality of memory blocks using the bad block management module, detect secondary bad blocks by performing a secondary bad block scan operation on normal memory blocks other than the primary bad blocks among the plurality of memory blocks, and register the detected primary bad blocks and the detected secondary bad blocks as bad blocks.

Abstract: An apparatus for controlling a memory device may include: a table storing information of a plurality of read voltages; an error correction unit suitable for correcting an error of read data; and a processor functionally coupled to the RR table and the error correction unit. The processor selects a default read voltage among the plurality of read voltages from the table when a read fail for the memory device is recognized, sets a shift direction of the default read voltage based on the number of read cells of the memory device read by the default read voltage, and controls a read retry operation of the memory device based on at least one read voltage in the set shift direction in the table.

Abstract: An apparatus for controlling a memory device may include: a table storing information of a plurality of read voltages; an error correction unit suitable for correcting an error of read data; and a processor functionally coupled to the RR table and the error correction unit. The processor selects a default read voltage among the plurality of read voltages from the table when a read fail for the memory device is recognized, sets a shift direction of the default read voltage based on the number of read cells of the memory device read by the default read voltage, and controls a read retry operation of the memory device based on at least one read voltage in the set shift direction in the table.

Abstract: Provided are novel dihydro-1H-phosphole 1-oxide derivatives and a preparation method thereof. More particularly, the dihydro-1H-phosphole 1-oxide derivatives include 1,3-dihydro-1H-2,1-oxaphosphole 1-oxide derivatives and 2,3-dihydro-1H-2,1-azaphosphole 1-oxide derivatives. Further, in the preparation method of a dihydro-1H-phosphole 1-oxide derivative according to the present invention, various phosphinine oxide derivatives may be prepared with high yield by a simple synthesis process by reacting a phosphinic derivative and a vinyl derivative with each other in the presence of a rhodium (Rh) catalyst, an oxidant, and a base.