Abstract: Present invention relates to a semiconductor device including a buried gate structure. A semiconductor device comprises a substrate; a first fluorine-containing layer over the substrate; a trench formed in the first fluorine-containing layer and extended into the substrate; a gate dielectric layer formed over the trench; a gate electrode formed over the gate dielectric layer and filling a portion of the trench; a second fluorine-containing layer formed over the gate electrode; and a fluorine-containing passivation layer between the gate dielectric layer and the gate electrode.

Abstract: The present disclosure relates to a polyamide molding composition including a semi-aromatic, semi-crystalline copolyamide and flat glass fibers that shows a low tendency to absorb moisture and thus maintains its excellent mechanical and optical properties also during storage and/or use.

Abstract: A battery monitoring system includes a data receiver configured to receive battery information data and vehicle information data from a data collecting device connected to a vehicle, a battery management score calculator configured to calculate, based on the battery information data and the vehicle information data, factors affecting battery degradation among a charging habit, a driving habit, and a parking habit of a user, calculate, based on the factors, a battery management score, and store the battery management score in a database, and an information transmitter configured to transmit the battery management score to a terminal.

Abstract: A battery ledger management system, includes: a data collecting unit receiving battery production information from an external source, and receiving battery information data and vehicle information data from a data collecting device; a battery ID generation and management unit generating a unique battery ID for each battery unit based on the battery production information; a state information generation and management unit generating and managing state information, information on a current usage state of the battery for the battery ID of each battery unit using the battery information data and the vehicle information data; and a usage information generation and management unit generating and managing usage information, information on a usage history of the battery for the battery ID of each battery unit using the battery information data and the vehicle information data.

Abstract: Present invention is related to a semiconductor device with an improved reliability and a method for the same. A method for fabricating a semiconductor device according to an embodiment of the present invention may comprise: forming a plurality of bit line structures over a substrate; forming line-shaped openings between the bit line structures; forming a stopper structure on edges of the line-shaped openings; filling a line pattern in each of the line-shaped openings; forming a plurality of contact plugs and a plurality of isolation grooves by etching the line patterns; and filling a plug isolation layer in the isolation grooves.

Abstract: Various example embodiments provide a computer system of unsupervised learning with deep similarity for optical flow estimation and a method thereof. According to various example embodiments, the computer system may be configured to calculate deep similarity by using deep features extracted from a sequence of a plurality of images, and learn optical flow for the images based on the deep similarity. In other words, the computer system may learn deep learning model for estimating optical flow through unsupervised learning based on deep similarity for a sequence of a plurality of images. At this time, the computer system may learn optical flow by using a feature separation loss function obtained by dividing occlusion locations and non-occlusion locations on the deep similarity map.

Abstract: A method for fabricating a semiconductor device includes: forming an insulating layer over a substrate including a cell region and a peripheral region; forming an opening in the insulating layer by selectively etching the insulating layer in the cell region; forming a plug conductive layer to fill the opening and cover the insulating film; etching the plug conductive layer and the insulating layer in the peripheral region by using a peri-open mask covering the cell region; trimming the peri-open mask to expose the plug conductive layer in a boundary region where the cell region and the peripheral region contact each other; etching the plug conductive layer in the boundary region by using the trimmed peri-open mask; forming a peri-gate conductive layer over the entire surface of the substrate; and etching the peri-gate conductive layer by using a cell open mask.

Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.

Abstract: A memory system includes a memory controller including: a memory core configured to store data and an error correction code corresponding to the data; a syndrome generator configured to generate a first syndrome by substituting the data and the error correction code, read from the memory core, into a first check matrix, and generate a second syndrome by substituting the data and the error correction code, read from the memory core, into a second check matrix; and an error correction unit configured to correct an error of the read data and error correction code by using the first syndrome and the second syndrome, wherein constituents having values of ‘1’ in the first check matrix have values of ‘1’ also in the second check matrix.

Abstract: An unmanned aerial vehicle has a main body, a plurality of propeller connection parts extending from at least one side surface of the main body by a specific length, a plurality of propellers respectively connected to ends of the plurality of propeller connection parts, and a plurality of cameras mounted on at least one surface of the main body. A first camera interposed between the plurality of propeller connection parts among the plurality of cameras is disposed spaced from a center point of the main body by a distance of a first size. A first virtual straight line connecting a center point of a first propeller disposed adjacent to the first camera among the plurality of propellers to a center point of the main body has a length of a second size.

Abstract: An apparatus and a method for detecting a fault location of an underground cable are proposed. The apparatus includes: an optimal reference signal design unit configured to design a reference signal for detecting the fault location of the underground cable considering propagation characteristics of the underground cable according to a time-frequency domain reflectometry method; a signal application and acquisition unit configured, as the designed reference signal is generated and applied to the underground cable, to acquire the reference signal applied to the underground cable and a reflected signal of the applied reference signal; and a data analysis unit configured to analyze whether a fault location of the underground cable exists according to a decision on similarity between the reference signal and the reflected signal after obtaining a time-frequency domain energy distribution for the acquired reference signal and reflected signal.

Abstract: A semiconductor device test socket has a shielding structure formed around each contactor so as to prevent signal delay or distortion during a test process and thereby enhance the test reliability. The socket includes a vertical probe comprising a contactor which has a contact terminal to be electrically connected to an external connection terminal of a semiconductor device. The shielding structure which is formed by laminating a conductive material on the outer edge of the contactor and is electrically connected to a ground. The socket further includes an elastic layer which is filled in the space between the contactor and the shielding structure, and surrounds the contactor such that the contact terminal of the contactor is exposed; and a connection film which is formed by laminating a conductive material so as to electrically connect shielding structures of multiple vertical probes.

Abstract: Described herein is a polyamide composition (P) including specific flat glass fibres (B) with elongated shape having a non-circular cross-sectional area. The polyamide composition (P) is advantageously used for the production of molded parts. Also described herein is a method of using molded parts obtainable by molding of the polyamide composition (P) to produce mechanical parts. The molded parts are characterized by having improved fatigue resistance properties. Also described herein is a polyamide composition (P) including PA 6.6 as polyamide (A) and flat glass fibres (B).

Abstract: A semiconductor device test socket, wherein a shielding structure is formed around each contactor so as to prevent signal delay or distortion during a test process and thereby enhance the test reliability, is proposed. The test socket can include: a vertical probe having a contactor which has a contact terminal to be electrically connected to an external connection terminal of a semiconductor device, and a shielding structure which is formed by laminating a conductive material on the outer edge of the contactor and is electrically connected to a ground; and an elastic layer which is filled in the space between the contactor and the shielding structure, and surrounds the contactor such that the contact terminal of the contactor is exposed.

Abstract: The present technology provides pyrrolidine and piperidine compounds or pharmaceutically acceptable salts thereof, preparation processes thereof, pharmaceutical compositions comprising the same, and uses thereof. In particular, said compounds may be usefully applied in the treatment and prevention of FAP-mediated diseases.

Abstract: According to an embodiment of the present disclosure, a system for supporting a skin treatment using ultrasound comprises a treatment map management unit configured to determine an ultrasonic treatment map of at least one of a treatment intensity, a treatment number and a treatment depth for at least one skin section of a user with reference to skin condition information including information about at least one of moisture content and wrinkles of the user's skin; a guide providing unit configured to provide the user with a guide for treatment based on the determined ultrasonic treatment map; and a monitoring management unit configured to monitor whether the user follows the guide with reference to treatment action information of the user according to the provided guide.

Abstract: A memory system includes a memory controller including: a memory core configured to store data and an error correction code corresponding to the data; a syndrome generator configured to generate a first syndrome by substituting the data and the error correction code, read from the memory core, into a first check matrix, and generate a second syndrome by substituting the data and the error correction code, read from the memory core, into a second check matrix; and an error correction unit configured to correct an error of the read data and error correction code by using the first syndrome and the second syndrome, wherein constituents having values of ‘1’ in the first check matrix have values of ‘1’ also in the second check matrix.

Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

Abstract: A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

Abstract: An unmanned aerial vehicle has a main body, a plurality of propeller connection parts extending from at least one side surface of the main body by a specific length, a plurality of propellers respectively connected to ends of the plurality of propeller connection parts, and a plurality of cameras mounted on at least one surface of the main body. A first camera interposed between the plurality of propeller connection parts among the plurality of cameras is disposed spaced from a center point of the main body by a distance of a first size. A first virtual straight line connecting a center point of a first propeller disposed adjacent to the first camera among the plurality of propellers to a center point of the main body has a length of a second size.