Abstract: A method and a device for synthesizing a background and a face by considering a face shape and using a deep learning network are proposed. The method and the device are characterized to receive an input of an original image and a converted face image, remove a central part from the original image, remove edges so that a central part remains in the converted face image, and then extract a feature vector from each image to perform image synthesis.

Abstract: Provided is a method of stacking media in a media storage unit, which includes: receiving information about a length of a medium entering a media storage unit; calculating a delay time of a stopper corresponding to the length of the medium; and applying a delay time of the stopper calculated for each medium entering the media storage unit to differentially control activation of the stopper for each medium.

Abstract: The present invention relates to a method and an apparatus for composing a background and a face by using a deep learning network, comprising: receiving an input of an original face image and a converted face image, and extracting data preprocessing and feature vectors for each image; generating a face feature vector mask from the extracted feature vectors; and generating a composite image by performing adaptive object normalization on the basis of the generated face feature vector mask.

Abstract: A memory device and operating method of the memory device are provided. The memory device comprises a memory cell storing data based on a first voltage, a row decoder selecting a wordline of the memory cell based on the first voltage, and a wordline predecoder configured to generate a “predec” signal, which is for generating a wordline voltage to be provided to the row decoder. The wordline predecoder is driven by the first voltage and a second voltage, which is different from the first voltage, receives a row address signal, associated with selecting the wordline, and an internal clock signal associated with adjusting operating timings of elements included in the memory device. The wordline predecoder performs a NAND operation on the row address signal and the internal clock signal, and provides the “predec” signal generated based on a result of the NAND operation to the row decoder.

Abstract: The present invention relates to a method and an apparatus for composing a background and a face by using a deep learning network, comprising: receiving an input of an original face image and a converted face image, and extracting data preprocessing and feature vectors for each image; generating a face feature vector mask from the extracted feature vectors; and generating a composite image by performing adaptive object normalization on the basis of the generated face feature vector mask.

Abstract: A method and a device for synthesizing a background and a face by considering a face shape and using a deep learning network are proposed. The method and the device are characterized to receive an input of an original image and a converted face image, remove a central part from the original image, remove edges so that a central part remains in the converted face image, and then extract a feature vector from each image to perform image synthesis.

Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

Abstract: A memory device is provided. The memory device comprises an internal clock generator configured to receive an external clock signal from a host and generate an internal clock signal in accordance with a chip enable signal, an internal enable signal generator configured to operate based on the internal clock signal and receive an external enable signal from the host and generate an internal enable signal, and a monitoring signal generator configured to output a monitoring signal that is generated based on at least one of the internal clock signal or the internal enable signal to the host.

Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

Abstract: A developing composition and a method of forming a pattern using the same are provided. According to embodiments of inventive concepts, the developing composition may include at least one repeating unit selected from a first repeating unit represented by Chemical Formula A1 a second repeating unit represented by Chemical Formula A2, or both the first repeating unit represented by Chemical Formula A1 and second repeating unit represented by Chemical Formula A2. The developing composition may further include a copolymer including a third repeating unit represented by Chemical Formula A3.

Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming an etch-target layer, a mask layer, a blocking layer, and a photoresist layer, which are sequentially stacked on a substrate; forming a photoresist pattern, the forming the photoresist pattern including irradiating the photoresist layer with extreme ultraviolet (EUV) light; forming a mask layer, the forming the mask layer including etching the mask layer using the photoresist pattern as an etch mask; and forming a target pattern, the forming the target pattern including etching the etch-target layer using the mask pattern as an etch mask. The photoresist layer may include an organic metal oxide. The blocking layer may be a non-polar layer and may limit and/or prevent a metallic element in the photoresist layer from infiltrating into the mask layer.

Abstract: A substrate inspection apparatus generates, when anomalies of a plurality of second solder pastes among a plurality of first solder pastes printed on a first substrate is detected, at least one image indicating a plurality of second solder pastes with anomalies detected by using an image about a first substrate, applies the at least one image to a machine-learning-based model, acquires a plurality of first values indicating relevance of respective first fault types to the at least one image and a plurality of first images indicating regions associated with one of a plurality of first fault types, determines a plurality of second fault types, which are associated with the plurality of second solder pastes by using the plurality of first values and the plurality of first images, and determines at least one third solder paste, which is associated with the respective second fault types.

Abstract: A memory device and operating method of the memory device are provided. The memory device comprises a memory cell storing data based on a first voltage, a row decoder selecting a wordline of the memory cell based on the first voltage, and a wordline predecoder configured to generate a “predec” signal, which is for generating a wordline voltage to be provided to the row decoder. The wordline predecoder is driven by the first voltage and a second voltage, which is different from the first voltage, receives a row address signal, associated with selecting the wordline, and an internal clock signal associated with adjusting operating timings of elements included in the memory device. The wordline predecoder performs a NAND operation on the row address signal and the internal clock signal, and provides the “predec” signal generated based on a result of the NAND operation to the row decoder.

Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.

Abstract: A memory device is provided. The memory device comprises an internal clock generator configured to receive an external clock signal from a host and generate an internal clock signal in accordance with a chip enable signal, an internal enable signal generator configured to operate based on the internal clock signal and receive an external enable signal from the host and generate an internal enable signal, and a monitoring signal generator configured to output a monitoring signal that is generated based on at least one of the internal clock signal or the internal enable signal to the host.

Abstract: An apparatus, a recording medium, and a method for generating a control parameter of a screen printer are disclosed. The apparatus includes a memory that stores a simulation model configured to derive predictive inspection information on a printed state of solder paste based on a plurality of control parameters of the screen printer; a communication circuit configured to receive first inspection information on a plurality of solder pastes printed by the screen printer based on a first control parameter, and a processor electrically connected to the memory and the communication circuit.

Abstract: The present disclosure relates to a transit transfer path unit structure connecting a supply/collection cassette and a banknote transfer path of an upper main body in an ATM which includes the upper main body and a lower main body and has a structure in which the supply/collection cassette is mounted on one side of the lower main body. The transit transfer path unit is disposed on one side of the upper main body of the ATM, and detachably provided between the supply/collection cassette and the banknote transfer path provided in the upper main body for separation from a banknote transfer route. Thus, the upper main body may be easily pulled to the front or rear of the ATM without any interference with the transit transfer path unit to perform the maintenance work, enhancing the convenience of the maintenance of the ATM.

Abstract: A substrate inspection apparatus generates, when anomalies of a plurality of second solder pastes among a plurality of first solder pastes printed on a first substrate is detected, at least one image indicating a plurality of second solder pastes with anomalies detected by using an image about a first substrate, applies the at least one image to a machine-learning-based model, acquires a plurality of first values indicating relevance of respective first fault types to the at least one image and a plurality of first images indicating regions associated with one of a plurality of first fault types, determines a plurality of second fault types, which are associated with the plurality of second solder pastes by using the plurality of first values and the plurality of first images, and determines at least one third solder paste, which is associated with the respective second fault types.

Abstract: The present disclosure relates to a transit transfer path unit structure connecting a supply/collection cassette and a banknote transfer path of an upper main body in an ATM which includes the upper main body and a lower main body and has a structure in which the supply/collection cassette is mounted on one side of the lower main body. The transit transfer path unit is disposed on one side of the upper main body of the ATM, and detachably provided between the supply/collection cassette and the banknote transfer path provided in the upper main body for separation from a banknote transfer route. Thus, the upper main body may be easily pulled to the front or rear of the ATM without any interference with the transit transfer path unit to perform the maintenance work, enhancing the convenience of the maintenance of the ATM.

Abstract: An apparatus, a recording medium, and a method for generating a control parameter of a screen printer are disclosed. The apparatus includes a memory that stores a simulation model configured to derive predictive inspection information on a printed state of solder paste based on a plurality of control parameters of the screen printer; a communication circuit configured to receive first inspection information on a plurality of solder pastes printed by the screen printer based on a first control parameter, and a processor electrically connected to the memory and the communication circuit.