Patents by Inventor Tae-Min Eom

Tae-Min Eom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8138057
    Abstract: A metal oxide alloy layer comprises a first layer including a first metal oxide and having a first thickness, and a second layer formed on the first layer, the second layer including a second metal oxide and having a second thickness, wherein a value of the first thickness is such that the first metal oxide is allowed to move into the second layer and a value of the second thickness is such that the second metal oxide is allowed to move into the first layer to form a single-layered structure in which the first and second metal oxides are mixed.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: March 20, 2012
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Jung-Ho Lee, Jung-Sik Choi, Jun-Hyun Cho, Tae-Min Eom, Ji-Hyun Lee
  • Publication number: 20080305591
    Abstract: A metal oxide alloy layer comprises a first layer including a first metal oxide and having a first thickness, and a second layer formed on the first layer, the second layer including a second metal oxide and having a second thickness, wherein a value of the first thickness is such that the first metal oxide is allowed to move into the second layer and a value of the second thickness is such that the second metal oxide is allowed to move into the first layer to form a single-layered structure in which the first and second metal oxides are mixed.
    Type: Application
    Filed: August 22, 2008
    Publication date: December 11, 2008
    Inventors: Jung-Ho LEE, Jung-sik Choi, Jun-hyun Cho, Tae-min Eom, Ji-hyun Lee
  • Patent number: 7427573
    Abstract: A metal oxide alloy layer comprises a first layer including a first metal oxide and having a first thickness, and a second layer formed on the first layer, the second layer including a second metal oxide and having a second thickness, wherein a value of the first thickness is such that the first metal oxide is allowed to move into the second layer and a value of the second thickness is such that the second metal oxide is allowed to move into the first layer to form a single-layered structure in which the first and second metal oxides are mixed.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: September 23, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ho Lee, Jung-Sik Choi, Jun-Hyun Cho, Tae-Min Eom, Ji-Hyun Lee
  • Patent number: 7310140
    Abstract: In a method and an apparatus for inspecting a wafer surface, a wafer is loaded into a chamber. An incident light including a first light for sensing a vertical position of the wafer and a second light for inspecting the wafer surface is irradiated onto the wafer. The first light is reflected on an inspection region or a next inspection region of the wafer and is detected to control a wafer position. The second light is scattered on the inspection region and is detected to inspect the wafer surface of the inspection region. Position information of a wafer is examined and a position of the wafer is adjusted before inspecting a surface of inspection region of a wafer so as to enable accurate inspection of the wafer surface.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: December 18, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Min Eom, Yu-Sin Yang, Chung-Sam Jun, Yun-Jung Jee, Joung-Soo Kim, Moon-Kyung Kim, Sang-Mun Chon, Sun-Yong Choi
  • Publication number: 20070188185
    Abstract: A method of inspecting a leakage current of a dielectric layer on a substrate including a cell array region having a plurality of cell blocks including a patterned structure, the dielectric layer formed on the patterned structure, and a peripheral circuit region includes depositing a corona ion charge on a cell block selected from the plurality of cell blocks and measuring a variance of a surface voltage caused by a leakage current through the dielectric layer on the selected cell block. The variance of the surface voltage is compared with reference data to determine a leakage current characteristic of the dielectric layer.
    Type: Application
    Filed: February 26, 2007
    Publication date: August 16, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Tae-Min Eom, Chung-Sam Jun, Yu-Sin Yang, Yun-Jung Jee
  • Patent number: 7186280
    Abstract: A method of inspecting a leakage current of a dielectric layer on a substrate including a cell array region having a plurality of cell blocks including a patterned structure, the dielectric layer formed on the patterned structure, and a peripheral circuit region includes depositing a corona ion charge on a cell block selected from the plurality of cell blocks and measuring a variance of a surface voltage caused by a leakage current through the dielectric layer on the selected cell block. The variance of the surface voltage is compared with reference data to determine a leakage current characteristic of the dielectric layer.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: March 6, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Min Eom, Chung-Sam Jun, Yu-Sin Yang, Yun-Jung Jee
  • Publication number: 20060157694
    Abstract: A metal oxide alloy layer comprises a first layer including a first metal oxide and having a first thickness, and a second layer formed on the first layer, the second layer including a second metal oxide and having a second thickness, wherein a value of the first thickness is such that the first metal oxide is allowed to move into the second layer and a value of the second thickness is such that the second metal oxide is allowed to move into the first layer to form a single-layered structure in which the first and second metal oxides are mixed.
    Type: Application
    Filed: January 9, 2006
    Publication date: July 20, 2006
    Inventors: Jung-Ho Lee, Jung-Sik Choi, Jun-Hyun Cho, Tae-Min Eom, Ji-Hyun Lee
  • Publication number: 20060022698
    Abstract: A method of inspecting a leakage current of a dielectric layer on a substrate including a cell array region having a plurality of cell blocks including a patterned structure, the dielectric layer formed on the patterned structure, and a peripheral circuit region includes depositing a corona ion charge on a cell block selected from the plurality of cell blocks and measuring a variance of a surface voltage caused by a leakage current through the dielectric layer on the selected cell block. The variance of the surface voltage is compared with reference data to determine a leakage current characteristic of the dielectric layer.
    Type: Application
    Filed: July 7, 2005
    Publication date: February 2, 2006
    Inventors: Tae-Min Eom, Chung-Sam Jun, Yu-Sin Yang, Yun-Jung Jee
  • Patent number: 6927077
    Abstract: An apparatus for measuring contamination of a semiconductor substrate includes a chuck for loading a substrate, a position detection means for recognizing a front surface of the loaded substrate to obtain position data of a portion of the substrate to be measured, a first driving part for moving the chuck in accordance with the position data to measure a rear portion of the substrate, and a surface measurement means disposed under the chuck for selectively measuring metal contamination of the substrate at the rear portion of the substrate. In operation, the substrate is loaded onto a chuck, position data of a portion of the substrate to be measured is obtained by recognizing patterns formed on the substrate, the substrate is then moved in accordance with the position data to measure a rear portion of the substrate, and metal contamination is selectively measured at the rear portion of the substrate.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: August 9, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Min Eom, Yu-Sin Yang, Kwan-Woo Ryu, Park-Song Kim, Sang-Mun Chon, Sun-Yong Choi, Chung-Sam Jun
  • Patent number: 6869215
    Abstract: A method and apparatus for detecting contaminants in an ion-implanted wafer by annealing and activating the ion-implanted wafer by heating or charging or both, and measuring the thermal wave absorbance generated from the activated wafer.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: March 22, 2005
    Assignee: Samsung Electrics, Co., LTD
    Inventors: Yu-Sin Yang, Sang-Mun Chon, Sun-Yong Choi, Chung Sam Jun, Kwan-Woo Ryu, Park-Song Kim, Tae-Min Eom
  • Publication number: 20040263836
    Abstract: In a method and an apparatus for inspecting a wafer surface, a wafer is loaded into a chamber. An incident light including a first light for sensing a vertical position of the wafer and a second light for inspecting the wafer surface is irradiated onto the wafer. The first light is reflected on an inspection region or a next inspection region of the wafer and is detected to control a wafer position. The second light is scattered on the inspection region and is detected to inspect the wafer surface of the inspection region. Position information of a wafer is examined and a position of the wafer is adjusted before inspecting a surface of inspection region of a wafer so as to enable accurate inspection of the wafer surface.
    Type: Application
    Filed: June 25, 2004
    Publication date: December 30, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Tae-Min Eom, Yu-Sin Yang, Chung-Sam Jun, Yun-Jung Jee, Joung-Soo Kim, Moon-Kyung Kim, Sang-Mun Chon, Sun-Yong Choi
  • Patent number: 6803241
    Abstract: A method of monitoring contact holes of an integrated circuit using corona charges is provided for determining whether the contact holes are open. The method includes transmitting corona charges over a unit chip having contact holes on a semiconductor wafer; measuring the surface voltage of the unit chip; making a graph illustrating a relationship between the amount of corona charges transmitted and the measured surface voltage of the unit chip; and analyzing the graph to determine whether the contact holes of the unit chip are open. According to the method of the present invention, contact holes may be monitored at an in-line state when manufacturing an integrated circuit by transmitting corona charges onto a unit chip, eliminating the need to use a scanning electronic microscope, thereby preventing a reduction in yield.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: October 12, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-min Eom, Chung-sam Jun, Yu-sin Yang
  • Publication number: 20040105486
    Abstract: A method and apparatus for detecting contaminants in an ion-implanted wafer by annealing and activating the ion-implanted wafer by heating or charging or both, and measuring the thermal wave absorbance generated from the activated wafer.
    Type: Application
    Filed: May 29, 2003
    Publication date: June 3, 2004
    Inventors: Yu-Sin Yang, Sang-Mun Chon, Sun-Yong Choi, Chung Sam Jun, Kwan-Woo Ryu, Park-Song Kim, Tae-Min Eom
  • Publication number: 20040100298
    Abstract: An apparatus for measuring contamination of a semiconductor substrate includes a chuck for loading a substrate, a position detection means for recognizing a front surface of the loaded substrate to obtain position data of a portion of the substrate to be measured, a first driving part for moving the chuck in accordance with the position data to measure a rear portion of the substrate, and a surface measurement means disposed under the chuck for selectively measuring metal contamination of the substrate at the rear portion of the substrate. In operation, the substrate is loaded onto a chuck, position data of a portion of the substrate to be measured is obtained by recognizing patterns formed on the substrate, the substrate is then moved in accordance with the position data to measure a rear portion of the substrate, and metal contamination is selectively measured at the rear portion of the substrate.
    Type: Application
    Filed: November 12, 2003
    Publication date: May 27, 2004
    Inventors: Tae-Min Eom, Yu-Sin Yang, Kwan-Woo Ryu, Park-Song Kim, Sang-Mun Chon, Sun-Yong Choi, Chung-Sam Jun
  • Publication number: 20030129776
    Abstract: A method of monitoring contact holes of an integrated circuit using corona charges is provided for determining whether the contact holes are open. The method includes transmitting corona charges over a unit chip having contact holes on a semiconductor wafer; measuring the surface voltage of the unit chip; making a graph illustrating a relationship between the amount of corona charges transmitted and the measured surface voltage of the unit chip; and analyzing the graph to determine whether the contact holes of the unit chip are open. According to the method of the present invention, contact holes may be monitored at an in-line state when manufacturing an integrated circuit by transmitting corona charges onto a unit chip, eliminating the need to use a scanning electronic microscope, thereby preventing a reduction in yield.
    Type: Application
    Filed: January 9, 2003
    Publication date: July 10, 2003
    Inventors: Tae-min Eom, Chung-sam Jun, Yu-sin Yang