Patents by Inventor Tae O. Jung

Tae O. Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9252223
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed, in which a buried gate region is formed, a nitride film spacer is formed at sidewalls of the buried gate region, and the spacer is etched in an active region in such a manner that the spacer remains in a device isolation region. Thus, if a void occurs in the device isolation region, the spacer can prevent a short-circuit from occurring between the device isolation region and its neighboring gates.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: February 2, 2016
    Assignee: SK HYNIX INC.
    Inventor: Tae O Jung
  • Patent number: 9024409
    Abstract: A semiconductor device and a method for forming the same are disclosed. In a method for forming the semiconductor substrate including a cell region and a peripheral region, a guard pattern defined by an epitaxial growth layer located at the edge part between the cell region and the peripheral region is formed. As the guard pattern is not damaged by an oxidation process, a bias leakage path between an N-well bias and a P-well bias of the peripheral region is prevented from occurring Reliability of a gate oxide film may be increased, resulting in an increased production yield of the semiconductor device and implementation of stable voltage and current characteristics.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventor: Tae O Jung
  • Publication number: 20150061004
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed, in which a buried gate region is formed, a nitride film spacer is formed at sidewalls of the buried gate region, and the spacer is etched in an active region in such a manner that the spacer remains in a device isolation region. Thus, if a void occurs in the device isolation region, the spacer can prevent a short-circuit from occurring between the device isolation region and its neighboring gates.
    Type: Application
    Filed: November 3, 2014
    Publication date: March 5, 2015
    Inventor: Tae O JUNG
  • Patent number: 8900967
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed, in which a buried gate region is formed, a nitride film spacer is formed at sidewalls of the buried gate region, and the spacer is etched in an active region in such a manner that the spacer remains in a device isolation region. Thus, if a void occurs in the device isolation region, the spacer can prevent a short-circuit from occurring between the device isolation region and its neighboring gates.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: December 2, 2014
    Assignee: SK Hynix Inc.
    Inventor: Tae O Jung
  • Publication number: 20140141593
    Abstract: A semiconductor device and a method for forming the same are disclosed. In a method for forming the semiconductor substrate including a cell region and a peripheral region, a guard pattern defined by an epitaxial growth layer located at the edge part between the cell region and the peripheral region is formed. As the guard pattern is not damaged by an oxidation process, a bias leakage path between an N-well bias and a P-well bias of the peripheral region is prevented from occurring Reliability of a gate oxide film may be increased, resulting in an increased production yield of the semiconductor device and implementation of stable voltage and current characteristics.
    Type: Application
    Filed: January 27, 2014
    Publication date: May 22, 2014
    Applicant: SK HYNIX INC.
    Inventor: Tae O. JUNG
  • Publication number: 20120273918
    Abstract: A semiconductor device and a method for forming the same are disclosed. In a method for forming the semiconductor substrate including a cell region and a peripheral region, a guard pattern defined by an epitaxial growth layer located at the edge part between the cell region and the peripheral region is formed. As the guard pattern is not damaged by an oxidation process, a bias leakage path between an N-well bias and a P-well bias of the peripheral region is prevented from occurring Reliability of a gate oxide film may be increased, resulting in an increased production yield of the semiconductor device and implementation of stable voltage and current characteristics.
    Type: Application
    Filed: January 10, 2012
    Publication date: November 1, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Tae O Jung
  • Patent number: 8129239
    Abstract: A semiconductor device is disclosed that stably ensures an area of a storage node contact connected to a junction region in an active region of the semiconductor device and is thus able to improve the electrical properties of the semiconductor device and enhance a yield, and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having an active region including a gate, a storage node contact region, and an isolation region that defines the active region. A passing gate and an isolation structure surrounding the passing gate are formed in the isolation region. A silicon epitaxial layer is selectively formed over an upper portion of the passing gate to expand the storage node contact region.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: March 6, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Tae O Jung
  • Publication number: 20110076835
    Abstract: A semiconductor device is disclosed that stably ensures an area of a storage node contact connected to a junction region in an active region of the semiconductor device and is thus able to improve the electrical properties of the semiconductor device and enhance a yield, and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having an active region including a gate, a storage node contact region, and an isolation region that defines the active region. A passing gate and an isolation structure surrounding the passing gate are formed in the isolation region. A silicon epitaxial layer is selectively formed over an upper portion of the passing gate to expand the storage node contact region.
    Type: Application
    Filed: December 8, 2010
    Publication date: March 31, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Tae O. JUNG
  • Patent number: 7872313
    Abstract: A semiconductor device is disclosed that stably ensures an area of a storage node contact connected to a junction region in an active region of the semiconductor device and is thus able to improve the electrical properties of the semiconductor device and enhance a yield, and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having an active region including a gate, a storage node contact region, and an isolation region that defines the active region. A passing gate and an isolation structure surrounding the passing gate are formed in the isolation region. A silicon epitaxial layer is selectively formed over an upper portion of the passing gate to expand the storage node contact region.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: January 18, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Tae O Jung
  • Publication number: 20100109075
    Abstract: A semiconductor device is disclosed that stably ensures an area of a storage node contact connected to a junction region in an active region of the semiconductor device and is thus able to improve the electrical properties of the semiconductor device and enhance a yield, and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having an active region including a gate, a storage node contact region, and an isolation region that defines the active region. A passing gate and an isolation structure surrounding the passing gate are formed in the isolation region. A silicon epitaxial layer is selectively formed over an upper portion of the passing gate to expand the storage node contact region.
    Type: Application
    Filed: December 30, 2008
    Publication date: May 6, 2010
    Inventor: Tae O JUNG
  • Patent number: 7358136
    Abstract: A method for manufacturing a semiconductor device includes expanding an active region and a recess region by an epitaxial growth process. As a result, a margin is sufficiently secured in processes for forming a device isolation film that defines the active region and for expanding a recess region to form a bulb recess region.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: April 15, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Tae O. Jung