Patents by Inventor Tae Seok Kwon

Tae Seok Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6583054
    Abstract: Provided with a method for forming conductive lines in a semiconductor device including the steps of: (a) forming a first conductive line on a substrate; (b) forming a first insulating layer on the substrate as well as on the first conductive line; (c) etching the first insulating layer on the first conductive line to form a first opening; (d) forming a second insulating layer on the first insulating layer to be in contact with the upper part of the first opening, thereby sealing the first opening; (e) etching the first and second insulating layers corresponding to the first conductive line to form a second opening and at the same time extend the first opening so as to expose the first conductive line; and (f) forming a second conductive line within the first and second openings so as to be connected with the first conductive line, thereby preventing halation caused by irregular reflection during exposure on the second photo resist because the second insulating layer has a less difference in thickness, and su
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: June 24, 2003
    Assignee: Hyundai Microelectronics Co., Ltd.
    Inventor: Tae-Seok Kwon
  • Patent number: 6548377
    Abstract: A method for forming a line of a semiconductor device is provided, which improves the life span of the line and its reliability by improving resistance to electromigration (EM).
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: April 15, 2003
    Assignee: Hynix Semiconductor Inc.
    Inventor: Tae Seok Kwon
  • Patent number: 6548410
    Abstract: A method of forming wires for semiconductor devices can restrict increase of a wires resistance and a contact resistance of the semiconductor device by forming a plug without generating a void or keyhole, and includes a step of forming an insulation film on lower wires, a step of forming a contact hole on the lower wires by selectively etching the insulation film, a step of performing a precleaning process by using an argon sputtering method until the lower wires at the lower portion of the contact hole are etched at a predetermined depth, a step of forming a plug by depositing a tungsten in the contact hole, and a step of forming upper wires on the plug and the second insulation film. A re-deposition layer consisting of a material of the lower wires is formed at the inner walls of the contact hole in the precleaning process, and thus a whole process is simplified by omitting a step of forming a glue layer or adhesion layer.
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: April 15, 2003
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Tae Seok Kwon
  • Publication number: 20020090807
    Abstract: A method for forming a line of a semiconductor device is provided, which improves the life span of the line and its reliability by improving resistance to electromigration (EM).
    Type: Application
    Filed: November 13, 2001
    Publication date: July 11, 2002
    Applicant: Hynix Semiconductor Inc.
    Inventor: Tae Seok Kwon
  • Publication number: 20020068461
    Abstract: A method of forming wires for semiconductor devices can restrict increase of a wires resistance and a contact resistance of the semiconductor device by forming a plug without generating a void or keyhole, and includes a step of forming an insulation film on lower wires, a step of forming a contact hole on the lower wires by selectively etching the insulation film, a step of performing a precleaning process by using an argon sputtering method until the lower wires at the lower portion of the contact hole are etched at a predetermined depth, a step of forming a plug by depositing a tungsten in the contact hole, and a step of forming upper wires on the plug and the second insulation film. A re-deposition layer consisting of a material of the lower wires is formed at the inner walls of the contact hole in the precleaning process, and thus a whole process is simplified by omitting a step of forming a glue layer or adhesion layer.
    Type: Application
    Filed: November 17, 1999
    Publication date: June 6, 2002
    Inventor: TAE SEOK KWON
  • Publication number: 20020064939
    Abstract: Provided with a method for forming conductive lines in a semiconductor device including the steps of: (a) forming a first conductive line on a substrate; (b) forming a first insulating layer on the substrate as well as on the first conductive line; (c) etching the first insulating layer on the first conductive line to form a first opening; (d) forming a second insulating layer on the first insulating layer to be in contact with the upper part of the first opening, thereby sealing the first opening; (e) etching the first and second insulating layers corresponding to the first conductive line to form a second opening and at the same time extend the first opening so as to expose the first conductive line; and (f) forming a second conductive line within the first and second openings so as to be connected with the first conductive line, thereby preventing halation caused by irregular reflection during exposure on the second photo resist because the second insulating layer has a less difference in thickness, and su
    Type: Application
    Filed: October 19, 1999
    Publication date: May 30, 2002
    Inventor: TAE-SEOK KWON