Abstract: The present disclosure relates to a high-entropy alloy and a manufacturing method therefor, and in particular, a high-entropy alloy and a manufacturing method therefor that comprises a multi-element alloy matrix and Cu, and comprises an alloy having a face-centered cubic (FCC)-based phase, such that the high-entropy alloy may have greater hardness and strength than an existing transition metal alloy while maintaining a FCC-based single phase, and has high lubricity.

Abstract: Provided are a polyimide-based film having excellent visibility, a film for a cover window, and a display device including the same.

Abstract: A quantum dot including a core that includes a first semiconductor nanocrystal including zinc and selenium, and optionally sulfur and/or tellurium, and a shell that includes a second semiconductor nanocrystal including zinc, and at least one of sulfur or selenium is disclosed. The quantum dot has an average particle diameter of greater than or equal to about 13 nm, an emission peak wavelength in a range of about 440 nm to about 470 nm, and a full width at half maximum (FWHM) of an emission wavelength of less than about 25 nm. A method for preparing the quantum dot, a quantum dot-polymer composite including the quantum dot, and an electronic device including the quantum dot is also disclosed.

Abstract: A quantum dot light-emitting device including first electrode and a second electrode, a quantum dot layer between the first electrode and the second electrode, a first electron transport layer and a second electron layer disposed between the quantum dot layer and the second electrode. The second electron transport layer is disposed between the quantum dot layer and the first electron transport layer, wherein each of the first electron transport layer and the second electron transport layer includes an inorganic material. A lowest unoccupied molecular orbital energy level of the second electron transport layer is shallower than a lowest unoccupied molecular orbital energy level of the first electron transport layer, and a lowest unoccupied molecular orbital energy level of the quantum dot layer is shallower than a lowest unoccupied molecular orbital energy level of the second electron transport layer. An electronic device including the quantum dot light-emitting device.

Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.

Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.

Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.

Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.

Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.

Abstract: A method for fabricating a semiconductor device includes: forming a gate trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the gate trench; forming a first work function layer over the gate dielectric layer; doping a work function adjustment element to form a second work function layer which overlaps with the sidewalls of the gate trench; forming a gate conductive layer that partially fills the gate trench; and forming doped regions inside the semiconductor substrate on both sides of the gate trench.

Abstract: A semiconductor device that has a passing gate with a single gate electrode and a main gate with lower and upper gate electrodes mitigates gate induced drain leakage (GIDL). Additional elements that help mitigate GIDL include the upper gate electrode having a lower work function than the lower gate electrode, and the lower gate electrode being disposed below a storage node junction region while the upper gate electrode is disposed at a same level as the storage node junction region.

Abstract: An armrest lock may include a lever coupled to one side of the sliding cover, a rod provided in the sliding cover such that one side thereof is coupled to the lever, a trigger coupled to the other side of the rod and configured to operate in response to a motion of the lever, and a locking element coupled to the opening door and the armrest body and configured to be unlocked from at least one of the opening door and the armrest body when coming into contact with the trigger.

Abstract: A method for forming a semiconductor structure includes forming a trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the trench; forming a work function layer over the gate dielectric layer; recessing the work function layer, and forming a gate electrode which is positioned in the trench; and exposing the gate electrode to a thermal process, and forming a dipole induction layer between the gate electrode and the gate dielectric layer.

Abstract: A method for forming a semiconductor structure includes forming a trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the trench; forming a work function layer over the gate dielectric layer; recessing the work function layer, and forming a gate electrode which is positioned in the trench; and exposing the gate electrode to a thermal process, and forming a dipole induction layer between the gate electrode and the gate dielectric layer.

Abstract: A method for forming a semiconductor structure includes forming a trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the trench; forming a work function layer over the gate dielectric layer; recessing the work function layer, and forming a gate electrode which is positioned in the trench; and exposing the gate electrode to a thermal process, and forming a dipole induction layer between the gate electrode and the gate dielectric layer.

Abstract: A method for forming a semiconductor structure includes forming a trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the trench; forming a work function layer over the gate dielectric layer; recessing the work function layer, and forming a gate electrode which is positioned in the trench; and exposing the gate electrode to a thermal process, and forming a dipole induction layer between the gate electrode and the gate dielectric layer.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.

Abstract: An embodiment of the semiconductor device includes a recess formed in an active region, a gate buried in a lower part of the recess, a first capping insulation film formed over the gate, a second capping insulation film formed over the first capping insulation film, and a third capping insulation film formed over the second capping insulation film. In the semiconductor device including the buried gate, mechanical stress caused by a nitride film can be reduced by reducing the volume of a nitride film in a capping insulation film formed over a buried gate, and the ratio of silicon to nitrogen of the nitride film is adjusted, so that mechanical stress is reduced, resulting in improvement of operation characteristics of the semiconductor device.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.

Abstract: An apparatus for opening and closing a sliding armrest console may include having a console body, an opening and closing plate rotatably secured to an upper portion of the console body to thereby open and close an upper surface of the console body, and an armrest slid from the opening and closing plate, may include a hook provided to a front end portion of the opening and closing plate and controlling opening and closing of the opening and closing plate from the console body, and a locking unit provided to the armrest, controlling a sliding operation of the armrest by a rotation operation and operating the hook together with the controlling of the sliding operation of the armrest at the same time.