Patents by Inventor Tae-Su Park

Tae-Su Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7868458
    Abstract: The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer; an epitaxially grown titanium silicide layer having a phase of C49 and formed on the exposed silicon substrate disposed within the contact hole; and a metal layer formed on an upper surface of the titanium silicide layer.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: January 11, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Moon-Keun Lee, Tae-Kwon Lee, Jun-Mo Yang, Tae-Su Park, Yoon-Jik Lee
  • Publication number: 20100169256
    Abstract: Disclosed herein is a separate learning system and method using a two-layered neural network having target values for hidden nodes. The separate learning system of the present invention includes an input layer for receiving training data from a user, and including at least one input node. A hidden layer includes at least one hidden node. A first connection weight unit connects the input layer to the hidden layer, and changes a weight between the input node and the hidden node. An output layer outputs training data that has been completely learned. The second connection weight unit connects the hidden layer to the output layer, changing a weight between the output and the hidden node, and calculates a target value for the hidden node, based on a current error for the output node.
    Type: Application
    Filed: March 12, 2010
    Publication date: July 1, 2010
    Applicant: INHA-INDUSTRY PARTNERSHIP INSTITUTE
    Inventors: Ju Hong Lee, Bum Ghi Choi, Tae Su Park
  • Patent number: 7734555
    Abstract: Disclosed herein is a separate learning system and method using a two-layered neural network having target values for hidden nodes. The separate learning system of the present invention includes an input layer for receiving training data from a user, and including at least one input node. A hidden layer includes at least one hidden node. A first connection weight unit connects the input layer to the hidden layer, and changes a weight between the input node and the hidden node. An output layer outputs training data that has been completely learned. The second connection weight unit connects the hidden layer to the output layer, changing a weight between the output and the hidden node, and calculates a target value for the hidden node, based on a current error for the output node.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: June 8, 2010
    Assignee: INHA-Industry Partnership Institute
    Inventors: Ju Hong Lee, Bum Ghi Choi, Tae Su Park
  • Publication number: 20090146306
    Abstract: The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer; an epitaxially grown titanium silicide layer having a phase of C49 and formed on the exposed silicon substrate disposed within the contact hole; and a metal layer formed on an upper surface of the titanium silicide layer.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 11, 2009
    Inventors: Moon-Keun Lee, Tae-Kwon Lee, Jun-Mo Yang, Tae-Su Park, Yoon-Jik Lee
  • Patent number: 7476617
    Abstract: The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer; an epitaxially grown titanium silicide layer having a phase of C49 and formed on the exposed silicon substrate disposed within the contact hole; and a metal layer formed on an upper surface of the titanium silicide layer.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: January 13, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Moon-Keun Lee, Tae-Kwon Lee, Jun-Mo Yang, Tae-Su Park, Yoon-Jik Lee
  • Publication number: 20070282772
    Abstract: Disclosed herein is a separate learning system and method using a two-layered neural network having target values for hidden nodes. The separate learning system of the present invention includes an input layer for receiving training data from a user, and including at least one input node. A hidden layer includes at least one hidden node. A first connection weight unit connects the input layer to the hidden layer, and changes a weight between the input node and the hidden node. An output layer outputs training data that has been completely learned. The second connection weight unit connects the hidden layer to the output layer, changing a weight between the output and the hidden node, and calculates a target value for the hidden node, based on a current error for the output node.
    Type: Application
    Filed: July 14, 2006
    Publication date: December 6, 2007
    Applicant: INHA-INDUSTRY PARTNERSHIP INSTITUTE
    Inventors: Ju Hong Lee, Bum Ghi Choi, Tae Su Park
  • Publication number: 20060157742
    Abstract: The present invention relates to a semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. This titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer; an epitaxially grown titanium silicide layer having a phase of C49 and formed on the exposed silicon substrate disposed within the contact hole; and a metal layer formed on an upper surface of the titanium silicide layer.
    Type: Application
    Filed: February 24, 2006
    Publication date: July 20, 2006
    Inventors: Moon-Keun Lee, Tae-Kwon Lee, Jun-Mo Yang, Tae-Su Park, Yoon-Jik Lee
  • Patent number: 7037827
    Abstract: A semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. The titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer. An epitaxially grown titanium silicide layer having a phase of C49 and is formed on the exposed silicon substrate disposed within the contact hole; and a metal layer is formed on an upper surface of the titanium silicide layer.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: May 2, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Moon-Keun Lee, Tae-Kwon Lee, Jun-Mo Yang, Tae-Su Park, Yoon-Jik Lee
  • Publication number: 20040180543
    Abstract: A semiconductor device with an epitaxially grown titanium silicide layer having a phase of C49 and a method for fabricating the same. The titanium silicide layer has a predetermined interfacial energy that does not transform the phase of the titanium layer, and thus, occurrences of agglomeration of the titanium layer and a grooving phenomenon can be prevented. The semiconductor device includes: a silicon layer; an insulation layer formed on the silicon layer, wherein a partial portion of the insulation layer is opened to form a contact hole exposing a partial portion of the silicon layer. An epitaxially grown titanium silicide layer having a phase of C49 and is formed on the exposed silicon substrate disposed within the contact hole; and a metal layer is formed on an upper surface of the titanium silicide layer.
    Type: Application
    Filed: December 30, 2003
    Publication date: September 16, 2004
    Inventors: Moon-Keun Lee, Tae-Kwon Lee, Jun-Mo Yang, Tae-Su Park, Yoon-Jik Lee