Abstract: In a method of fabricating a semiconductor device, a first sacrificial through-via is formed to fill a first via-hole extending from a first surface of a first substrate toward a second surface of the first substrate opposite the first surface. The first surface of the first substrate is bonded to a carrier. The first sacrificial through-via is exposed, and the first sacrificial through-via is selectively removed. After selectively removing the first sacrificial through-via, a conductive through-via is formed to fill the first via-hole.

Abstract: A semiconductor package has an improved solder joint reliability. The package includes a semiconductor chip having chip pads, and metal lines electrically coupled to the chip pads. The package further includes ball lands provided on a ball-forming surface and electrically coupled to the metal lines. A solder resist covers the ball-forming surface, and solder balls are formed on the respective ball lands. Each ball land has a first part facing a center of the ball-forming surface and a second part opposing the first part. The first part is covered with the solder resist and the second part is exposed to an opening defined by the solder resist.

Abstract: A semiconductor chip package includes a ground metal layer disposed in close proximity to a signal layer for carrying electrical input and output signals to and from the chip. The ground metal layer has a plate structure and is formed by two metal plates or a single metal plate having openings for the electrode pads of the chip. Because the ground trace is nearest to the signal trace, the loop area formed by a signal current and its return current is reduced and, therefore, loop inductance is reduced as well. Further, because of the plate structure of the ground trace and its proximity to the signal trace, the inductive element and parasitic parameters due to the signal trace can be significantly reduced and the electrical performance of high-frequency semiconductor IC devices is greatly improved, especially when applied to wafer level packaging IC devices.

Abstract: An electrical connection structure for electrically connecting a semiconductor chip to an external circuit device is provided. The connection structure comprises a ground conductive plate connected to ground power of the semiconductor chip; an insulating layer formed on the ground conductive plate; a signal pattern layer formed on the insulating layer and having signal patterns in electrical communication with the semiconductor chip. The ground conductive plate includes a projected blank pattern that is the complement of the signal pattern layer. With the present invention, self inductance and mutual inductance of the connection structure is reduced. Further, because of the blank patterns formed in the proximal ground plate, the capacitance is also reduced.

Abstract: A semiconductor chip package includes a ground metal layer disposed in close proximity to a signal layer for carrying electrical input and output signals to and from the chip. The ground metal layer has a plate structure and is formed by two metal plates or a single metal plate having openings for the electrode pads of the chip. Because the ground trace is nearest to the signal trace, the loop area formed by a signal current and its return current is reduced and, therefore, loop inductance is reduced as well. Further, because of the plate structure of the ground trace and its proximity to the signal trace, the inductive element and parasitic parameters due to the signal trace can be significantly reduced and the electrical performance of high-frequency semiconductor IC devices is greatly improved, especially when applied to wafer level packaging IC devices.

Abstract: An electrical connection structure for electrically connecting a semiconductor chip to an external circuit device is provided. The connection structure comprises a ground conductive plate connected to ground power of the semiconductor chip; an insulating layer formed on the ground conductive plate; a signal pattern layer formed on the insulating layer and having signal patterns in electrical communication with the semiconductor chip. The ground conductive plate includes a projected blank pattern that is the complement of the signal pattern layer. With the present invention, self inductance and mutual inductance of the connection structure is reduced. Further, because of the blank patterns formed in the proximal ground plate, the capacitance is also reduced.

Abstract: A substrate is configured to electrically interconnect a semiconductor chip to an external device. The substrate preferably includes a ground plane that is electrically interconnected to a ground power of the semiconductor chip. An insulating layer is attached to the ground plane. A pattern layer is attached to the insulating layer. The pattern layer includes signal patterns that communicate electrical signals with the semiconductor chip and ground patterns that are electrically interconnected to the ground plane. The ground patterns can include bonding lands to provide electrical connection to the semiconductor chip. The bonding lands can be further provided with first via holes that electrically interconnect the ground patterns to the ground plane.