Abstract: A disease network construction method includes the steps of: (1) organizing cohort data in time series; (2) stratifying or grouping the data organized in step (1) by confounding variables; (3) deriving a correlation of diseases within the stratification in step (2); and (4) constructing a disease network on the basis of the correlation derived in step (3). According to the present invention, a disease may be influenced by a variety of clinical and medical confounding variables such as age, gender, race, socioeconomic variables, and regional and national health care systems, and thus a method for more reliably deriving a correlation between diseases may be provided.

Abstract: Disclosed is a method of reading data from a memory including a NAND cell array for performing communications via a serial peripheral interface (SPI) bus. The method includes sequentially receiving inputs of a block address, a word-line address, and a bit-line address of the NAND cell array; and starting to output data written in the NAND cell array immediately after the bit-line address is completely input. In this case, the sequential receiving of the inputs is performed via one input terminal.

Abstract: A method of writing data in a memory comprising a NAND cell array is disclosed, wherein a data output device completes the writing process only by transmitting the data and a start address for writing the data to the memory.

Abstract: Disclosed is a method of reading data from a memory including a NAND cell array for performing communications via a serial peripheral interface (SPI) bus. The method includes sequentially receiving inputs of a block address, a word-line address, and a bit-line address of the NAND cell array; and starting to output data written in the NAND cell array immediately after the bit-line address is completely input. In this case, the sequential receiving of the inputs is performed via one input terminal.

Abstract: A method of writing data in a memory comprising a NAND cell array is disclosed, wherein a data output device completes the writing process only by transmitting the data and a start address for writing the data to the memory.

Abstract: The present invention relates to a bootstrap circuit. The present invention stably perform a read operation of a flash memory cell by constructing the bootstrap circuit to be clamped only at a high potential voltage ‘HVcc’ and to be normally operated at a low potential voltage source ‘LVcc’ to easily control on a word line boosting voltage, by sensing the high potential voltage source ‘HVcc’ and the low potential voltage source ‘LVcc’.

Abstract: The charge pump circuit, includes an amplifier, a condenser, and a modifying circuit. The amplifier has a plurality of first voltage transfer stages, and each first voltage transfer stage transfers a voltage from an input to an output thereof such that the output voltage equals the input voltage minus a voltage drop. The condenser increases the output voltage at the output of at least one of the voltage transfer stages, and the voltage modifying circuit modifies each increased output voltage to compensate for the voltage drop.

Abstract: A sense amplifier of a virtual ground flat cell is provided that prevents leakage currents. The sense amplifier includes a first through third current/voltage converters and a voltage comparator. The third current/voltage converter maintains electric potentials substantially equal between cells adjacent and nearby a selected cell being read. In particular, the third current/voltage converter maintains electric potentials between the low cells coupled to a ground terminal not selected as a bit line. The first current/voltage converter converts a current from the selected memory cell received via a bit line to a first voltage. The second current/voltage converter converts a reference current to a reference voltage. The voltage comparator compares the first and reference voltages to output a voltage corresponding to the data stored in the selected memory cell.

Abstract: A sense amplifier and method are provided using current/voltage converters that are suitable for a multibit (2 bit/cell) memory device. The sense amplifier includes first and second current/voltage converters and a voltage comparator. The current/voltage converters each include a current mirror amplification unit to amplify an input current and a current mirror conversion unit to convert the amplified current into a voltage. A current to be sensed is applied to the first current/voltage converter and a reference current is applied to the second current/voltage converter. The voltage comparator determines a voltage difference by comparing the voltage output by the first and second current/voltage converters. The sense amplifier and method increases the speed and ease of sensing the input current. Further, the sense amplifier and method applied to a multibit memory can reduce an area for memory elements by 40%.