Patents by Inventor Tae sun RYU

Tae sun RYU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9245899
    Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: January 26, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hauk Han, Yong-IL Kwon, JungSuk Oh, Tae sun Ryu, Jeonggil Lee
  • Publication number: 20150311298
    Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.
    Type: Application
    Filed: June 16, 2015
    Publication date: October 29, 2015
    Inventors: Hauk Han, Yong-IL Kwon, JungSuk Oh, Tae sun Ryu, Jeonggil Lee
  • Patent number: 9082653
    Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: July 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hauk Han, Yong-IL Kwon, JungSuk Oh, Tae sun Ryu, Jeonggil Lee
  • Publication number: 20150084109
    Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.
    Type: Application
    Filed: December 5, 2014
    Publication date: March 26, 2015
    Inventors: Hauk Han, Yong-IL Kwon, JungSuk Oh, Tae sun Ryu, Jeonggil Lee
  • Patent number: 8928092
    Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hauk Han, Yong-Il Kwon, JungSuk Oh, Tae sun Ryu, Jeonggil Lee
  • Publication number: 20140015030
    Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.
    Type: Application
    Filed: July 12, 2013
    Publication date: January 16, 2014
    Inventors: Hauk HAN, Yong-IL KWON, JungSuk OH, Tae sun RYU, Jeonggil LEE